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Takagi, Naofumi

Graduate School of Informatics, Department of Communications and Computer Engineering Professor

Takagi, Naofumi
list
    Last Updated :2022/05/14

    Basic Information

    Faculty

    • 工学部 工学部 情報学科

    Professional Memberships

    • 電子情報通信学会 学会誌編集委員会
    • 情報処理学会 アルゴリズム研究会
    • 電子情報通信学会 コンピュテーション研究専門委員会
    • IEEE Symposium on Computer Arithmetic Steering Committee
    • 電子情報通信学会 情報・システムソサエティ運営委員会
    • IEEE Transactions on Computers
    • 情報処理学会 システムLSI設計技術研究会
    • 情報処理学会 東海支部
    • 電子情報通信学会 ELEX編集委員会
    • 電子情報通信学会 東海支部
    • 電子情報通信学会 ディペンダブルコンピューティング研究専門委員会
    • IEEE
    • 日本情報科教育学会
    • 情報処理学会
    • 電子情報通信学会
    • IEEE Symposium on Computer Arithmetic Steering Committee
    • IEEE Transactions on Computers
    • IEEE

    Academic Degree

    • 工学修士(京都大学)
    • 工学博士(京都大学)

    Academic Resume (Graduate Schools)

    • 京都大学, 大学院工学研究科修士課程情報工学専攻, 修了

    Academic Resume (Undergraduate School/Majors)

    • 京都大学, 工学部情報工学科, 卒業

    High School

    • High School

      大阪府立 北野高等学校

    Research History

    • From Apr. 2010, To Present
      Kyoto University, 情報学研究科, 教授
    • From Apr. 2003, To Mar. 2010
      - 名古屋大学, 情報科学研究科, 教授
    • From May 1998, To Mar. 2003
      Nagoya University, 工学研究科, 教授
    • From 1998, To 2003
      Professor, Graduate School of Engineering, Nagoya University
    • From 2003
      - Professor, Graduate School of Information Science, Nagoya University
    • From Jun. 1994, To May 1998
      Nagoya University, School of Engineering, 助教授
    • From 1994, To 1998
      Associate Professor, School of Engineering, Nagoya University
    • From Apr. 1991, To May 1994
      Kyoto University, Faculty of Engineering, 助教授
    • From 1991, To 1994
      Associate Professor, Faculty of Engineering, Kyoto University
    • From Apr. 1984, To Mar. 1991
      Kyoto University, Faculty of Engineering, 助手
    • From 1984, To 1991
      Instructor, Faculty of Engineering, Kyoto University

    Language of Instruction

    • English

    ID,URL

    Website(s) (URL(s))

    researchmap URL

    list
      Last Updated :2022/05/14

      Research

      Research Topics, Overview of the research

      • Research Topics

        Parallel computing architecture, arithmetic circuits, hardware algorithms

      Research Interests

      • 論理設計
      • 論理回路
      • 算術演算回路
      • ハードウェアアルゴリズム
      • Logic design
      • Logic circuits
      • Arithmetic circuits
      • Hardware algorithm

      Research Areas

      • Informatics, Information networks
      • Informatics, Computer systems

      Papers

      • A Timing Fault Model and an Efficient Timing Fault Simulation Method for Rapid Single-Flux-Quantum Logic Circuits
        Shogo Nakamura; Kazuyoshi Takagi; Nobutaka Kito; Naofumi Takagi
        Journal of Physics: Conference Series, 30 Jul. 2021
      • Rapid Single-Flux-Quantum Logic Circuits Using Clockless Gates
        Takahiro Kawaguchi; Kazuyoshi Takagi; Naofumi Takagi
        IEEE Transactions on Applied Superconductivity, Jun. 2021, Peer-reviewed
      • A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs
        Takashi Dejima; Kazuyoshi Takagi; Naofumi Takagi
        IEEE Transactions on Applied Superconductivity, Oct. 2020, Peer-reviewed
      • Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        IEEE Transactions on Applied Superconductivity, Oct. 2020, Peer-reviewed
      • A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits
        K Kitamura; K Takagi; N Takagi
        Journal of Physics: Conference Series, Jul. 2020, Peer-reviewed
      • mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices
        Takase Hideki; Mori Tomoya; Takagi Kazuyoshi; Takagi Naofumi
        Journal of Information Processing, 2020
      • mROS: A lightweight runtime environment of ROS 1 nodes for embedded devices
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        Journal of Information Processing, 2020
      • mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        J. Inf. Process., 2020
      • Supporting TOPPERS/ASP3 Kernel to mROS to improve its capability
        Hiroi Imanishi; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019), Nov. 2019, Peer-reviewed
      • A functionality expansion of the lightweight runtime environment mROS for user defined message types
        Hidetosh Yugen; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        Asia Pacific Conference on Robot IoT System Development and Platform (APRIS2019), Nov. 2019, Peer-reviewed
      • Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        IPSJ Transactions on System LSI Design Methodology, Aug. 2019, Peer-reviewed
      • Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Using the Characteristics of Pulse Logic
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        ISEC 2019 - International Superconductive Electronics Conference, Jul. 2019, Peer-reviewed
      • Concurrent Error Detectable Carry Select Adder with Easy Testability
        KITO Nobutaka; TAKAGI Naofumi
        IEEE Transactions on Computers, Jul. 2019, Peer-reviewed
      • MROS: A lightweight runtime environment for robot software components onto embedded devices
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        ACM International Conference Proceeding Series, 06 Jun. 2019
      • mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON HIGHLY EFFICIENT ACCELERATORS AND RECONFIGURABLE TECHNOLOGIES (HEART), 2019
      • mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        2019
      • A Global Routing Method with Wire Length Budgeting for SFQ Logic Cirduits
        KITAMURA Kei; TAKAGI Kazuyoshi; TAKAGI Naofumi
        12th Superconducting SFQ VLSI Workshop (SSV 2019), Jan. 2019
      • A Hierarchical Placement Method with Cell Clustering for Rapid-Single-Flux-Quantum Ciercuits
        DEJIMA Takashi; TAKAGI Kazuyoshi; TAKAGI Naofumi
        12th Superconducting SFQ VLSI Workshop (SSV 2019), Jan. 2019
      • Encoder/Decoder for the Compound Signal of Data and Clock
        KAWAGUCHI Takahiro; TAKAGI Kazuyoshi; TAKAGI Naofumi
        12th Superconducting SFQ VLSI Workshop (SSV 2019), Jan. 2019
      • Core State Aware Slack Gathering Scheduling for Embedded Real-Time Systems
        MATSUI Kentaro; TAKASE Hideki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Asia Pacific Conference on Robot IoT System Development and Platform 2018, Oct. 2018
      • A motion planning method for mobile robot considering rotational motion in area coverage task
        Yano Taiki; TAKASE Hideki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Asia Pacific Conference on Robot IoT System Development and Platform 2018, Oct. 2018
      • Work-in-Progress: Design Concept of a Lightweight Runtime Environment for Robot Software Components onto Embedded Devices
        TAKASE Hideki; MORI Tomoya; TAKAGI Kazuyoshi; TAKAGI Naofumi
        International Conference on Embedded Software 2018, Sep. 2018, Peer-reviewed
      • A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        IEEE Transactions on Applied Superconductivity, 01 Jun. 2018, Peer-reviewed
      • A Generation Method of EUC-Hardware-Dependent Description of Complex Device Drivers in AUTOSAR
        HIROSE Hideki; TAKASE Hideki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        IPSJ ESW2017 Research Papers, Mar. 2018, Peer-reviewed
      • Algorithms for evaluating the matrix polynomial I + A + A2 + ⋯ + AN-1 with Reduced Number of Matrix Multiplications
        Kotaro Matsumoto; Kazuyoshi Takagi; Naofumi Takagi
        IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Feb. 2018, Peer-reviewed
      • High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic
        Ryo Sato; Yuki Hatanaka; Yuki Ando; Masamitsu Tanaka; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2017, Peer-reviewed, Invited
      • 32 x 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors
        Guang-Ming Tang; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Apr. 2017, Peer-reviewed
      • Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication
        Nobutaka Kito; Kazushi Akimoto; Naofumi Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Mar. 2017, Peer-reviewed
      • Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors
        TAKAGI Naofumi; TAKAGI Kazuyoshi; KITO Nobutaka
        10th Superconducting SFQ VLSI Workshop (SSV 2017), Feb. 2017
      • Demonstration of stored program computing in a 50-GHz SFQ microprocessor with embedded memories
        FUJIMAKI Akira; SATO Ryo; HATANAKA Yuki; AKAIKE Hiroyuki; TAKAGI Kazuyoshi; TAKAGI Naofumi; TANAKA Masamitsu
        10th Superconducting SFQ VLSI Workshop (SSV 2017), Feb. 2017
      • Static timing analysis of rapid single-flux-quantum circuits
        KAWAGUCHI Takahiro; TAKAGI KAzuyoshi; TAKAGI Naofumi
        The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), Oct. 2016, Peer-reviewed
      • Fast length-matching routing for rapid single flux quantum circuits
        KITO Nobutaka; TAKAGI Kazuyoshi; TAKAGI Naofumi
        The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016), Oct. 2016, Peer-reviewed
      • Extension of a logic simulation system for simulation-based verification of RSFQ logic circuits
        KITO Nobutaka; MATSUMOTO Gentoku; TAKAGI Kazuyoshi; TAKAGI Naofumi
        9th Superconducting SFQ VLSI Workshop (SSV 2016), Aug. 2016
      • A microarchitecture of an RSFQ 4-bit bit-slice 32-bit processor
        Tang Guanming; TAKAGI Kazuyoshi; TAKAGI Naofumi
        9th Superconducting SFQ VLSI Workshop (SSV 2016), Aug. 2016
      • Eight-bit bit-serial RSFQ microprocessor with minimal instruction set architecturefor demonstration programs
        SATO Ryo; TANAKA Masamitsu; HATANAKA Yuki; FUJIMAKI Akira; AKAIKE Hiroyuki; TAKAGI Naofumi; TAKAGI Kazuyoshi
        9th Superconducting SFQ VLSI Workshop (SSV 2016), Aug. 2016
      • Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4
        Yuki Ando; Ryo Sato; Masamitsu Tanaka; Kazuyoshi Takagi; Naofumi Takagi; Akira Fujimaki
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Aug. 2016, Peer-reviewed
      • High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
        Masamitsu Tanaka; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Jun. 2016, Peer-reviewed
      • RSFQ 4-bit Bit-Slice Integer Multiplier
        Guang-Ming Tang; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Jun. 2016, Peer-reviewed
      • Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Apr. 2016, Peer-reviewed
      • An Evaluation Framework of OS-Level Power Managements for the big. LITTLE Architecture
        Hideki Takase; Kazumi Aono; Yutaka Matsubara; Kazuyoshi Takagi; Naofumi Takagi
        2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2016, Peer-reviewed
      • 4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors
        Guang-Ming Tang; Kensuke Takata; Masamitsu Tanaka; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jan. 2016, Peer-reviewed
      • A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model
        Takahiro Kawaguchi; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2015, Peer-reviewed
      • Logic Design of Pattern Matching Circuit Based on Systolic Architecture Using Single-Flux-Quantum Circuits
        OHATA Masaya; UEDA Keita; TAKAGI Kazuyoshi; TAKAGI Naofumi
        8th Superconducting SFQ VLSI Workshop (SSV 2015), Jul. 2015
      • High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits
        Xizhu Peng; Qiuyun Xu; Faichi Kato; Yuki Yamanashi; Nobuyuki Yoshikawa; Akira Fujimaki; Naofumi Takagi; Kazuyoshi Takagi; Mutsuo Hidaka
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2015, Peer-reviewed, Invited
      • Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2015, Peer-reviewed
      • An allocation optimization method for partially-reliable scratch-pad memory in embedded systems
        Takuya Hatayama; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        IPSJ Transactions on System LSI Design Methodology, 01 Feb. 2015, Peer-reviewed
      • Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories
        Ryo Sato; Kensuke Takata; Masamitsu Tanaka; Akira Fujimaki; Naofumi Takagi; Kazuyoshi Takagi
        2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015, Peer-reviewed
      • Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories
        Masamitsu Tanaka; Kensuke Takata; Ryo Sato; Akira Fujimaki; Takahiro Kawaguchi; Yuki Ando; Kazuyoshi Takagi; Naofumi Takagi; Nobuyuki Yoshikawa
        2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015, Peer-reviewed
      • Demonstration of an 8-bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells
        Takahiro Kawaguchi; Masamitsu Tanaka; Kazuyoshi Takagi; Naofumi Takagi
        2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015, Peer-reviewed
      • A 4-bit Bit-Slice Multiplier for a 32-bit RSFQ Microprocessor
        Guang-Ming Tang; Kazuyoshi Takagi; Naofumi Takagi
        2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015, Peer-reviewed
      • 80-GHz Operation of an 8-bit RSFQ Arithmetic Logic Unit
        Yuki Ando; Ryo Sato; Masamitsu Tanaka; Kazuyoshi Takagi; Naofumi Takagi
        2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015, Peer-reviewed
      • PTL Routing Environment for SFQ Circuits Using a Commercial Router
        T. Kawaguchi; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Design of an 8-bit Bit-Serial SFQ Microprocessor CORE e4 with Four Registers
        Y. Ando; M. Tanaka; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Design of Shift-Register Memories for SFQ Micro Processors COREe
        R. Numaguchi; T. Takahashi; N. Yoshikawa; Y. Yamanashi; A. Fujimaki; M. Tanaka; N. Takagi; K. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Design and Implementation of Bit-Serial SFQ Microprocessor CORE e3
        R. Sato; K. Takata; M. Tanaka; A. Fujimaki; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Demonstration of 4-Bit-Parallel Bit-Slice ALU
        K. Takata; M. Tanaka; A. Fujimaki; G. Tang; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Minimum Depth Logic Circuits for Five-Variable Logic Functions Using Tree-Input Majority Gates
        M. Moriya; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Comparison of Bit-Slice Arithmetic Logic Units for 32-bit RSFQ Microprocessors
        G. Tang; K. Takagi; N. Takagi
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Design of RSFQ Microprocessors Integrated with RAMs Based on Bit-Serial Processing
        M. Tanaka; K. Takata; R. Satoh; A. Fujimaki; T. Kawaguchi; Y. Ando; K. Takagi; N. Takagi; N. Yoshikawa
        7th Superconducting SFQ VLSI Workshop (SSV 2014), Dec. 2014
      • Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis
        Akihiro Suda; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2014, Peer-reviewed
      • Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10 kA/cm(2) Nb Process
        Xizhu Peng; Yuki Yamanashi; Nobuyuki Yoshikawa; Akira Fujimaki; Naofumi Takagi; Kazuyoshi Takagi; Mutsuo Hidaka
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2014, Peer-reviewed
      • Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors
        Akira Fujimaki; Masamitsu Tanaka; Ryo Kasagi; Katsumi Takagi; Masakazu Okada; Yuhi Hayakawa; Kensuke Takata; Hiroyuki Akaike; Nobuyuki Yoshikawa; Shuichi Nagasawa; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2014, Peer-reviewed, Invited
      • Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
        Kazuyoshi Takagi; Nobutaka Kito; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2014, Peer-reviewed, Invited
      • A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits
        Hiroshi Kataoka; Hiroaki Honda; Farhad Mehdipour; Nobuyuki Yoshikawa; Akira Fujimaki; Hiroyuki Akaike; Naofumi Takagi; Kazuaki Murakami
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2014, Peer-reviewed, Invited
      • Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation
        Shuichi Nagasawa; Kenji Hinode; Tetsuro Satoh; Mutsuo Hidaka; Hiroyuki Akaike; Akira Fujimaki; Nobuyuki Yoshikawa; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2014, Peer-reviewed, Invited
      • An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality
        Kazumi Aono; Atsushi Iwata; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS), 2014, Peer-reviewed
      • An Allocation Optimization Method for Partially-Reliable Instruction Scratch-Pad Memory in Embedded Systems
        Takuya Hatayama; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2014, Peer-reviewed
      • A Design Framework for SFQ Circuits Using Clockless Gates
        T. Kawaguchi; K. Takagi; N. Takagi
        6th Superconducting SFQ VLSI Workshop (SSV 2013), Nov. 2013
      • Logical Design of Bit-Slice Barrel Shifter for 32-bit SFQ Microprocessors
        Y. Ohmomo; K. Takagi; N. Takagi
        6th Superconducting SFQ VLSI Workshop (SSV 2013), Nov. 2013
      • Design and Implementations of Component Circuits for RSFQ Bit-Slice Microprocessors
        M. Tanaka; Y. Hayakawa; K. Takata; A. Fujimaki; Y. Ohmomo; T. Kawaguchi; K. Takagi; N. Takagi
        6th Superconducting SFQ VLSI Workshop (SSV 2013), Nov. 2013
      • Retiming of SFQ Logic Circuits for Reduction of Flip-Flops
        N. Kito; K. Takagi; N. Takagi
        6th Superconducting SFQ VLSI Workshop (SSV 2013), Nov. 2013
      • High-Level Synthesis for Nested Loop Kernels with Non-Uniform Dependencies
        SUDA Akihiro; TAKASE Hideki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), Oct. 2013, Peer-reviewed
      • Retiming of Single Flux Quantum Logic Circuits for Flip-Flop Reduction
        KITO Nobuyuki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Proceedings - 18th Workshop on Synthesis And System Integration Mixed Information technologies (SASIMI 2013), Oct. 2013, Peer-reviewed
      • Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication
        Nobutaka Kito; Naofumi Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Sep. 2013, Peer-reviewed
      • An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits
        Naofumi Takagi
        PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, Jan. 2013, Peer-reviewed
      • A buffering method for parallelized loop with non-uniform dependencies in high-level synthesis
        Akihiro Suda; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi
        Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2013, Peer-reviewed
      • 60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm(2) Nb Process
        T. Kato; Y. Yamanashi; N. Yoshikawa; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa
        2013 IEEE 14TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2013, Peer-reviewed
      • Low Frequency Test of 4x4 Reconfigurable Data-Path Processors
        Y. Hayakawa; K. Takata; M. Okada; A. Fujimaki; M. Tanaka; H. Akaike; N. Yoshikawa; S. Nagasawa; N. Takagi
        5th Superconducting SFQ VLSI Workshop (SSV 2012), Dec. 2012
      • Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm2 Nb Process
        X. Peng; Y. Yamanashi; N. Yoshikawa; A. Fujimaki; K. Takagi; N. Takagi; S. Nagasawa
        5th Superconducting SFQ VLSI Workshop (SSV 2012), Dec. 2012
      • A High-Throughput SFQ Logarithm Computing Circuit Using the Radix-2 Signed-Digit Representation
        M. Tanaka; K. Takagi; N. Takagi
        5th Superconducting SFQ VLSI Workshop (SSV 2012), Dec. 2012
      • Measurement of an SFQ Half-Precision Floating-Point Adder Using the 10 kA/cm2 Nb Process
        T. Kato; N. Yoshikawa; A. Fujimaki; N. Takagi; K. Takagi; S. Nagasawa
        5th Superconducting SFQ VLSI Workshop (SSV 2012), Dec. 2012
      • A Logic Extraction Method Based on Periodical Pulse Arrival Model for Formal Verification of SFQ Circuits
        T. Kawaguchi; k. Takagi; N. Takagi
        5th Superconducting SFQ VLSI Workshop (SSV 2012), Dec. 2012
      • Fast inversion algorithm in GF(2(m)) suitable for implementation with a polynomial multiply instruction on GF(2)
        K. Kobayashi; N. Takagi; K. Takagi
        IET COMPUTERS AND DIGITAL TECHNIQUES, May 2012, Peer-reviewed
      • A C-Testable Multiple-Block Carry Select Adder
        Nobutaka Kito; Shinichi Fujii; Naofumi Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Apr. 2012, Peer-reviewed
      • A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
        Kazuhiro Nakamura; Ryo Shimazaki; Masatoshi Yamamoto; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2012, Peer-reviewed
      • Timing-Aware Description Methods and Gate-Level Simulation for Single Flux Quantum Circuits
        Nobutaka Kito; Kazuyoshi Takagi; Naofumi Takagi
        Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), Mar. 2012, Peer-reviewed
      • Backward Multiple Time-Frame Expansion for Accelerating Sequential SAT
        Kousuke Torii; Kazuhiro Nakamura; Kazuyoshi Takagi; Naofumi Takagi
        Proceedings - 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), Mar. 2012, Peer-reviewed
      • Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme
        Irina Kataeva; Hiroyuki Akaike; Akira Fujimaki; Nobuyuki Yoshikawa; Naofumi Takagi
        SUPERCONDUCTIVITY CENTENNIAL CONFERENCE 2011, 2012, Peer-reviewed
      • Design of SFQ Circuits Using Clockless Logic Gates
        T. Kawaguchi; K. Takagi; N. Takagi
        4th Superconducting SFQ VLSI Workshop (SSV 2011), Nov. 2011
      • Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits
        N. Kito; K. Takagi; N. Takagi
        4th Superconducting SFQ VLSI Workshop (SSV 2011), Nov. 2011
      • Design Algorithms for Superconducting SFQ Logic Circuits
        K. Takagi; N. Takagi
        4th Superconducting SFQ VLSI Workshop (SSV 2011), Nov. 2011
      • Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm(2) Nb Process
        Toshiki Kainuma; Yasuhiro Shimamura; Fumishige Miyaoka; Yuki Yamanashi; Nobuyuki Yoshikawa; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi; Shuichi Nagasawa
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2011, Peer-reviewed
      • Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor
        Irina Kataeva; Hiroyuki Akaike; Akira Fujimaki; Nobuyuki Yoshikawa; Shuichi Nagasawa; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2011, Peer-reviewed
      • 100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm(2) Niobium Process
        Masamitsu Tanaka; Hiroyuki Akaike; Akira Fujimaki; Yuki Yamanashi; Nobuyuki Yoshikawa; Shuichi Nagasawa; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2011, Peer-reviewed
      • Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
        Kazuyoshi Takagi; Yuki Ito; Shota Takeshima; Masamitsu Tanaka; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2011, Peer-reviewed
      • Partial product generation utilizing the sum of operands for reduced area parallel multipliers
        Hirotaka Kawashima; Naofumi Takagi
        IPSJ Transactions on System LSI Design Methodology, 2011, Peer-reviewed
      • Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers
        Kawashima Hirotaka; Takagi Naofumi
        Information and Media Technologies, 2011
      • A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
        Nobutaka Kito; Kensuke Hanai; Naofumi Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Oct. 2010, Peer-reviewed
      • A High-Speed VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Recognition Systems
        Ryo Shimazaki; Kazuhiro Nakamura; Masatoshi Yamamoto; Kazuyoshi Takagi; Naofumi Takagi
        Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), Oct. 2010, Peer-reviewed
      • A Verification Method of Pipeline Processing Behavior of Superconducting Single-Flux-Quantum Pulse Logic Circuits
        Kazuyoshi Takagi; Motoki Sato; Masamitsu Tanaka; Naofumi Takagi
        Proceedings - 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), Oct. 2010, Peer-reviewed
      • 100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm(2) Nb Multi-Layer Process
        Yuki Yamanashi; Toshiki Kainuma; Nobuyuki Yoshikawa; Irina Kataeva; Hiroyuki Akaike; Akira Fujimaki; Masamitsu Tanaka; Naofumi Takagi; Shuichi Nagasawa; Mutsuo Hidaka
        IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2010, Peer-reviewed
      • Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm
        Masamitsu Tanaka; Koji Obata; Yuki Ito; Shota Takeshima; Motoki Sato; Kazuyoshi Takagi; Naofumi Takagi; Hiroyuki Akaike; Akira Fujimaki
        IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2010, Peer-reviewed
      • Comparisons of Synchronous-Clocking SFQ Adders
        Naofumi Takagi; Masamitsu Tanaka
        IEICE TRANSACTIONS ON ELECTRONICS, Apr. 2010, Peer-reviewed
      • A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
        Kazuhiro Nakamura; Masatoshi Yamamoto; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Feb. 2010, Peer-reviewed
      • A Verification Method for Pipeline Processing Behavior of Single-Flux-Quantum Circuits by Equivalence Checking of Timed Logic Formulae
        M. Sato; M. Tanaka; K. Takagi; N. Takagi
        3rd Superconducting SFQ VLSI Workshop (SSV 2010), Jan. 2010
      • Minimization of SFQ Floating-Point Processing Units Using Variable-length Shift-registers
        M. Tanaka; K. Takagi; N. Takagi
        3rd Superconducting SFQ VLSI Workshop (SSV 2010), Jan. 2010
      • Timing Optimization Methods for Superconducting SFQ Circuits
        K. Takagi; S. Takeshima; M. Sato; M. Tanaka; N. Takagi
        3rd Superconducting SFQ VLSI Workshop (SSV 2010), Jan. 2010
      • High-Speed Floating-Point Processors based on Single-Flux-Quantum Circuit Technology
        N. Yoshikawa; T. Kainuma; H. Park; Y. Yamanashi; A. Fujimaki; N. Takagi; K. Takagi
        Asian Conference of Applied Superconductivity and Cryogenics (ACASC 2009), 07 Dec. 2009, Peer-reviewed, Invited
      • Component Design and Test of 50-GHz Half-Precision Floating-Point Adders and Multipliers
        N. Yoshikawa; T. Kainuma; H. Park; Y. Yamanashi; A. Fujimaki; N. Takagi; K. Takagi
        EUROFLUX 2009 International Conference, 22 Sep. 2009, Peer-reviewed, Invited
      • Recent Developments in Floating-Point Processors using Single-Flux-Quantum Circuits
        N. Yoshikawa; H. Park; H. Hara; Y. Yamanashi; A. Fujimaki; K. Takagi; N. Takagi; M. Hidaka
        9th European Conference on Applied Superconductivity (EUCAS 2009), 15 Sep. 2009, Peer-reviewed, Invited
      • Fast Hardware Algorithm for Division in GF(2(m)) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions
        Katsuki Kobayashi; Naofumi Takagi
        IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Aug. 2009, Peer-reviewed
      • New Nb multi-layer fabrication process for large-scale SFQ circuits
        S. Nagasawa; T. Satoh; K. Hinode; Y. Kitagawa; M. Hidaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi; N. Yoshikawa
        PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, Aug. 2009, Peer-reviewed
      • Design of single flux quantum cells for a 10-Nb-layer process
        H. Akaike; M. Tanaka; K. Takagi; I. Kataeva; R. Kasagi; A. Fujimaki; K. Takagi; M. Igarashi; H. Park; Y. Yamanashi; N. Yoshikawa; K. Fujiwara; S. Nagasawa; M. Hidaka; N. Takagi
        PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, Aug. 2009, Peer-reviewed
      • Testability of Multipliers with a Partial Product Compressor Consisting of Carry Save Adders
        KITO Nobutaka; TAKAGI Naofumi
        Transactions of IEICE, Jul. 2009, Peer-reviewed
      • A Crossbar Switch for Routing of 2-bit Wide Data Streams
        I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi
        Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), 15 Jun. 2009, Peer-reviewed
      • High-Throughput Arithmetic Circuits based on Systolic Architecture for SFQ Reconfigurable Data-Path
        M. Tanaka; K. Takagi; N. Takagi; Y. Yamanashi; N. Yoshikawa
        Technical Program of Superconducting SFQ VLSI Workshop (SSV 2009), 15 Jun. 2009, Peer-reviewed
      • Research on Effective Moat Configuration for Nb Multi-Layer Device Structure
        Kan Fujiwara; Shuichi Nagasawa; Yoshihito Hashimoto; Mutsuo Hidaka; Nobuyuki Yoshikawa; Masamitsu Tanaka; Hiroyuki Akaike; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer
        Tetsuro Satoh; Kenji Hinode; Shuichi Nagasawa; Yoshihiro Kitagawa; Mutsuo Hidaka; Nobuyuki Yoshikawa; Hiroyuki Akaike; Akira Fujimaki; Kazuyoshi Takagi; Naofumi Takagi
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation
        Masamitsu Tanaka; Koji Obata; Kazuyoshi Takagi; Naofumi Takagi; Akira Fujimaki; Nobuyuki Yoshikawa
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders
        Heejoung Park; Yuki Yamanashi; Kazuhiro Taketomi; Nobuyuki Yoshikawa; Masamitsu Tanaka; Koji Obata; Yuki Ito; Akira Fujimaki; Naofumi Takagi; Kazuyoshi Takagi; Shuichi Nagasawa
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier
        Hiroshi Hara; Koji Obata; Heejoung Park; Yuki Yamanashi; Kazuhiro Taketomi; Nobuyuki Yoshikawa; Masamitsu Tanaka; Akira Fujimaki; N. Takagi; Kazuyoshi Takagi; S. Nagasawa
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor
        Irina Kataeva; Hiroyuki Akaike; Akira Fujimaki; Nobuyuki Yoshikawa; Naofumi Takagi; Koji Inoue; Hiroaki Honda; Kazuaki Murakami
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2009, Peer-reviewed
      • Hardware Algorithms for SFQ Arithmetic Circuits
        TAKAGI Naofumi; TANAKA Masamitsu; TAKAGI Kazuyoshi
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed, Invited
      • Demonstration of 2x3 Reconfigurable-Data-Path Processors with 14000 Josephson Junctions
        FUJIMAKI Akira; KASAGI Ryo; TAKAGI Katsumi; KATAEVA Irina; AKAIKE Hiroyuki; TANAKA Masamitsu; TAKAGI Naofumi; YOSHIKAWA Nobuyuki; MURAKAMI Kazuaki
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • Enhanced Flexibility of an Operand Routing Network for an SFQ-RDP Processor
        KATAEVA Irina; AKAIKE Hiroyuki; FUJIMAKI Akira; Yoshikawa Nobuyuki; TAKAGI Naofumi; MURAKAMI Kazuaki
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • Singl-Flux Quantum Cells and Circuits Based on a Nb Multi-Layer Process
        AKAIKE Hiroyuki; TANAKA Masamitsu; TAKAGI Katsumi; KATAEVA Irina; KASAGI Ryo; Itoh M; FUJIMAKI Akira; IGARASHI M; PARK H; YAMANASHI Yuki; YOSHIKAWA Nobuyuki; NAGASAWA Shuichi; HIDAKA Mutsuo; TAKAGI Kazuyoshi; TAKAGI Naofumi
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • An Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on the A* Algorithm
        TANAKA Masamitsu; OBATA Koji; ITO Yuki; TAKESHIMA Shota; SATO Motoki; TAKAGI Kazuyoshi; TAKAGI Naofumi; AKAIKE Hiroyuki; FUJIMAKI Akira
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • Nb Multi-Layer Device Fabrication Technology
        NAGASAWA Shuichi; SATOH Tetsuro; HINODE Kenji; KITAGAWA Yoshihiro; HIDAKA Mutsuo; AKAIKE Hiroyuki; FUJIMAKI Akira; TAKAGI Kazuyoshi; TAKAGI Naofumi; YOSHIKAWA Nobuyuki
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • Design and High-Speed Test of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10 kA/cm2 Nb Process
        KAINUMA Toshiki; PARK Heejoung; TAKETOMI Kazuhiro; HARA Hiroshi; YAMANASHI Yuki; YOSHIKAWA Nobuyuki; TANAKA Masamitsu; ITO Yuki; FUJIMAKI Akira; TAKAGI Naofumi; TAKAGI Kazuyoshi; NAGASAWA Shuichi
        12th International Superconductive Electronics Conference (ISEC 2009), Jun. 2009, Peer-reviewed
      • Small Area Multipliers Utilizing the Sum of Operands
        KAWASHIMA Hirotaka; TAKAGI Naofumi
        Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Mar. 2009, Peer-reviewed
      • Fast Division Circuit in GF(2m) Based on the Extended Euclid's Algorithm with Parallelization of Modular Reductions
        KOBAYASHI Katsuki; TAKAGI Naofumi
        Proceedings - 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Mar. 2009, Peer-reviewed
      • A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
        Koji Obata; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2008, Peer-reviewed
      • A Combined Circuit for Multiplication and Inversion in GF(2(m))
        Katsuki Kobayashi; Naofumi Takagi
        IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Nov. 2008, Peer-reviewed
      • Design Support of Digit-Recurrence Algorithms for Arithmetic Circuits
        KUMAZAWA Fumio; TAKAGI Naofumi
        Transactions of IEICE, Nov. 2008, Peer-reviewed
      • SFQ cell design for A Nb-10-layer process
        H. Akaike; M. Tanaka; K. Takagi; I. Kataeva; R. Kasagi; A. Fujimaki; K. Takagi; M.Igarashi; H. Park; Y. Yamanashi; N. Yoshikawa; K. Fujiwara; S. Nagasawa; M. Hidaka; N. Takagi
        Abstracts on 21th International Symposium on Superconductivity (ISS2008), Oct. 2008, Peer-reviewed
      • An operand routing network for an SFQ-RDP processor: new design and experimental results
        I. Kataeva; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami
        Abstracts on 21th International Symposium on Superconductivity (ISS2008), Oct. 2008, Peer-reviewed
      • A Design Method of Easily Testable Multipliers with Various Structures of Partial Product Adder
        KITO NobutakaTAKAGI Naofumi
        Transactions of IEICE, Oct. 2008, Peer-reviewed
      • Novel serial-parallel converter using SFQ logic circuits
        H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi
        PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, Sep. 2008, Peer-reviewed
      • Demonstration of an SFQ-Based Accelerator Prototype for a High-Performance Computer
        A. Fujimaki; S. Iwasaki; K. Takagi; R. Kasagi; I. Kataeva; H. Akaike; M. Tanaka; N. Takagi; N. Yoshikawa; K. Murakami
        2008 Applied Superconductivity Conference (ASC 2008), Aug. 2008, Peer-reviewed
      • Reduced Area Multipliers Based on Karatsuba Algorithm
        KAWASHIMA Hirotaka; SHIBAOKA Masayuki; TAKAGI Naofumi; TAKAGI KAzuyoshi
        Transactions of IEICE, Jul. 2008, Peer-reviewed
      • Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits
        Naofumi Takagi; Kazuaki Murakami; Akira Fujimaki; Nobuyuki Yoshikawa; Koji Inoue; Hiroaki Honda
        IEICE TRANSACTIONS ON ELECTRONICS, Mar. 2008, Peer-reviewed, Invited
      • New Nb multi-layer Fabrication Process for Superconducting SFQ VLSI Circuits
        S. Nagasawa; T. Satoh; K. Hinode; Y. Kitagawa; M. Hidaka; H. Akaike; A. Fujimaki; K. Takagi; N. Takagi; N. Yoshikawa
        Superconducting SFQ VLSI Workshop 2008, Mar. 2008
      • Demonstration of the key components of an SFQ Reconfigurable Data-Paths Processor: an Operand Routing Network and a 2×2 RDP prototype
        I. Kataeva; S. Iwasaki; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami
        Superconducting SFQ VLSI Workshop 2008, Mar. 2008
      • CORE1: Review and Recent Developments in Bit-serial SFQ Microprocessors
        M. Tanaka; K. Obata; Y. Yamanashi; H. Park; S. Iwasaki; K. Taketomi; K. Takagi; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa
        Superconducting SFQ VLSI Workshop 2008, Mar. 2008
      • Design and Implementation of the SFQ Floating Point Units
        H. Park; Y. Yamanashi; H. Hara; K. Taketomi; N. Yoshikawa; M. Tanaka; K. Obata; Y. Itou; A. Fujimaki; N. Takagi; K. Takagi
        Superconducting SFQ VLSI Workshop 2008, Mar. 2008
      • Design and Implementation of the SFQ Half-Precision Floating Point Adder
        H. Park; Y. Yamanashi; H. Hara; K. Taketomi; N. Yoshikawa; M. Tanaka; K. Obata; Y. Itou; A. Fujimaki; N. Takagi; K. Takagi
        Superconducting SFQ VLSI Workshop 2008, Mar. 2008
      • Bipartite modular multiplication method
        Marcelo E. Kaihara; Naofumi Takagi
        IEEE TRANSACTIONS ON COMPUTERS, Feb. 2008, Peer-reviewed
      • Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems
        Kazuhiro Nakamura; Masatoshi Yamamoto; Kazuyoshi Takagi; Naofumi Takagi
        Proceedings - IEEE International Symposium on Circuits and Systems, 2008, Peer-reviewed
      • Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems
        Kazuhiro Nakamura; Masatoshi Yamamoto; Kazuyoshi Takagi; Naofumi Takagi
        PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, Peer-reviewed
      • Level-testability of multi-operand adders
        Nobutaka Kito; Naofumi Takagi
        PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, Peer-reviewed
      • A method of sequential circuit synthesis using one-hot encoding for single-flux-quantum digital circuits
        Koji Obata; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON ELECTRONICS, Dec. 2007, Peer-reviewed
      • Design of a reconfigurable data-path prototype in the single-flux-quantum circuit
        S. Iwasaki; M. Tanaka; Y. Yamanashi; H. Park; H. Akaike; A. Fujimaki; N. Yoshikawa; N. Takagi; K. Murakami; H. Honda; K. Inoue
        SUPERCONDUCTOR SCIENCE & TECHNOLOGY, Nov. 2007, Peer-reviewed
      • Multufunctional Buffers Using SFQ Logic Circuits
        H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; K. Fujiwara; N. Takagi
        Abstracts on 20th International Symposium on Superconductivity (ISS2007), Nov. 2007, Peer-reviewed
      • Design and Implementation of Single-Flux-Quantum Floating-Point Adders
        Y. Yamanashi; H. Park; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi
        Extended Abstract of 11th International Superconductivity Conference,Washington DC, Jun. 2007, Peer-reviewed
      • Fast Bit-Serial Multipliers Using RSFQ Logic Circuits
        H. Park; Y. Yamanashi; K. Taketomi; N. Yoshikawa; A. Fujimaki; N. Takagi
        Extended Abstract of 11th International Superconductivity Conference, Washington DC, Jun. 2007, Peer-reviewed
      • Logic synthesis method for dual-rail RSFQ digital circuits using root-shared binary decision diagrams
        Koji Obata; Kazuyoshi Takagi; Naofumi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jan. 2007, Peer-reviewed
      • An algorithm for inversion in GF (2(m)) - Suitable for implementation using a polynomial multiply instruction on GF(2)
        Katsuki Kobayashi; Naofumi Takagi; Kazuyoshi Takagi
        18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2007, Peer-reviewed
      • A hardware algorithm for integer division using the SD2 representation
        Naofumi Takagi; Shunsuke Kadowaki; Kazuyoshi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Oct. 2006, Peer-reviewed
      • Single-flux-quantum integer multiplier with systolic array structure
        K. Obata; M. Tanaka; Y. Tashiro; Y. Kamiya; N. Irie; K. Takagi; N. Takagi; A. Fujimaki; N. Yoshikawa; H. Terai; S. Yorozu
        PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, Oct. 2006, Peer-reviewed
      • Development of High-speed Single-flux-quantum Microprocessors
        A. Fujimaki; M. Tanaka; N. Irie; S. Iwasaki; T. Yamada; N. Takagi; H. Park; Y. Yamanashi; N. Yoshikawa; H. Terai; S. Yorozu; Y. Takai
        on 19th International Symposium on Superconductivity (ISS2006), Oct. 2006, Peer-reviewed
      • Hardware algorithm for computing reciprocal of Euclidean norm of a 3-D vector
        Fumio Kumazawa; Naofumi Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jun. 2006, Peer-reviewed
      • New countermeasures against power analysis attacks for Koblitz curve cryptosystems
        Yong-hee Jang; Naofumi Takagi; Kazuyoshi Takagi; Yong-jin Kwon
        2006 INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND SECURITY, PTS 1 AND 2, PROCEEDINGS, 2006, Peer-reviewed
      • A VLSI algorithm for integer square-rooting
        Naofumi Takagi; Kazuyoshi Takagi
        2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2, 2006, Peer-reviewed
      • A hardware algorithm for modular multiplication/division based on the extended Euclidean algorithm
        ME Kaihara; N Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2005, Peer-reviewed
      • Advanced design approaches for SFQ logic circuits based on the binary decision diagram
        T Nishigai; M Ito; N Yoshikawa; K Obata; K Takagai; N Takagai; A Fujimaki; H Terai; S Yorozu
        IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, Jun. 2005, Peer-reviewed
      • Design Method of Dual-Rail RSFQ Logic Circuits Using 2x2-Join
        OBATA Koji; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Transactions of IEICE, Mar. 2005, Peer-reviewed
      • A hardware algorithm for modular multiplication/division
        ME Kaihara; N Takagi
        IEEE TRANSACTIONS ON COMPUTERS, Jan. 2005, Peer-reviewed
      • A hardware algorithm for integer division
        N Takagi; S Kadowaki; K Takagi
        17th IEEE Symposium on Computer Arithmetic, Proceedings, 2005, Peer-reviewed
      • Bipartite modular multiplication
        ME Kaihara; N Takagi
        CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 2005, Peer-reviewed
      • A Memory Efficient Scalable VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems
        NAKAMURA Kazuhiro; SAWADA Yuki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Proceedings - 2004 International SoC Design Conference, Oct. 2004, Peer-reviewed
      • Systematic IEEE rounding method for high-speed floating-point multipliers
        NT Quach; NF Takagi; MJ Flynn
        IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, May 2004, Peer-reviewed
      • Floating-Point Euclidean Norm Computing Circuit
        KUMAZAWA Fumio; TAKAGI Naofumi; TAKAUCHI Daisuke; TAKAGI Kazuyoshi
        Transactions of IEICE, Apr. 2003, Peer-reviewed
      • A VLSI algorithm for modular multiplication/division
        ME Kaihara; N Takagi
        16TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2003, Peer-reviewed
      • Digit-recurrence algorithm for computing reciprocal square-root
        N Takagi; D Matsuoka; K Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jan. 2003, Peer-reviewed
      • A VLSI algorithm for division in GF(2(m)) based on extended binary GCD algorithm
        Y Watanabe; N Takagi; K Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, May 2002, Peer-reviewed
      • A real-time lipreading LSI for word recognition
        K Nakamura; N Murakami; K Takagi; N Takagi
        2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 2002, Peer-reviewed
      • A fast algorithm for multiplicative inversion in GF(2(m)) using normal basis
        N Takagi; J Yoshiki; K Takagi
        IEEE TRANSACTIONS ON COMPUTERS, May 2001, Peer-reviewed
      • A digit-recurrence algorithm for cube rooting
        N Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, May 2001, Peer-reviewed
      • A hardware algorithm for computing reciprocal square root
        N Takagi
        ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2001, Peer-reviewed
      • A fast addition algorithm for elliptic curve arithmetic in GF(2(n)) using projective coordinates
        A Higuchi; N Takagi
        INFORMATION PROCESSING LETTERS, Dec. 2000, Peer-reviewed
      • A VLSI algorithm for computing the Euclidean norm of a 3D vector
        N Takagi; S Kuwahara
        IEEE TRANSACTIONS ON COMPUTERS, Oct. 2000, Peer-reviewed
      • Minimum cut linear arrangement of p-q dags for VLSI layout of adder trees
        K Takagi; N Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, May 1999, Peer-reviewed
      • A high-speed reduced-size adder under left-to-right input arrival
        N Takagi; T Horiyama
        IEEE TRANSACTIONS ON COMPUTERS, Jan. 1999, Peer-reviewed
      • Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector
        N Takagi; S Kuwahara
        14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, Peer-reviewed
      • Powering by a table look-up and a multiplication with operand modification
        N Takagi
        IEEE TRANSACTIONS ON COMPUTERS, Nov. 1998, Peer-reviewed
      • A VLSI algorithm for modular division based on the binary GCD algorithm
        N Takagi
        IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, May 1998, Peer-reviewed
      • O(n)-depth modular exponentiation circuit algorithm
        T Hamano; N Takagi; S Yajima; FP Preparata
        IEEE TRANSACTIONS ON COMPUTERS, Jun. 1997, Peer-reviewed
      • Efficient initial approximation for multiplicative division and square root by a multiplication with operand modification
        M Ito; N Takagi; S Yajima
        IEEE TRANSACTIONS ON COMPUTERS, Apr. 1997, Peer-reviewed
      • Generating a power of an operand by a table look-up and a multiplication
        N Takagi
        13TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1997, Peer-reviewed
      • Square rooting by iterative multiply-additions
        Masayuki Ito; Naofumi Takagi; Shuzo Yajima
        Information Processing Letters, 09 Dec. 1996, Peer-reviewed
      • A hardware algorithm for modular division based on the extended euclidean algorithm
        N Takagi
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Nov. 1996, Peer-reviewed
      • A MULTIPLE-PRECISION MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS
        N TAKAGI
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Oct. 1995, Peer-reviewed
      • Function evaluation by table look-up and addition
        H HASSLER; N TAKAGI
        PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 1995, Peer-reviewed
      • O(n)-depth circuit algorithm for modular exponentiation
        T HAMANO; N TAKAGI; S YAJIMA; FP PREPARATA
        PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 1995, Peer-reviewed
      • Efficient initial approximation and fast converging methods for division and square root
        M ITO; N TAKAGI; S YAJIMA
        PROCEEDINGS OF THE 12TH SYMPOSIUM ON COMPUTER ARITHMETIC, 1995, Peer-reviewed
      • A MODULAR INVERSION HARDWARE ALGORITHM WITH A REDUNDANT BINARY REPRESENTATION
        N TAKAGI
        IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Aug. 1993, Peer-reviewed
      • A MODULAR MULTIPLICATION ALGORITHM WITH TRIANGLE ADDITIONS
        N TAKAGI
        11TH SYMPOSIUM ON COMPUTER ARITHMETIC : PROCEEDINGS, 1993, Peer-reviewed
      • A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM FOR MODULAR EXPONENTIATION
        N TAKAGI
        IEEE TRANSACTIONS ON COMPUTERS, Aug. 1992, Peer-reviewed
      • MODULAR MULTIPLICATION HARDWARE ALGORITHMS WITH A REDUNDANT REPRESENTATION AND THEIR APPLICATION TO RSA CRYPTOSYSTEM
        N TAKAGI; S YAJIMA
        IEEE TRANSACTIONS ON COMPUTERS, Jul. 1992, Peer-reviewed
      • Computational Power of a Memory-Based Parallel Computation Model with Content Addressable Memory
        TAKENAGA Yasuhiko; TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IPSJ, Apr. 1992, Peer-reviewed
      • REDUNDANT CORDIC METHODS WITH A CONSTANT SCALE FACTOR FOR SINE AND COSINE COMPUTATION
        N TAKAGI; T ASADA; S YAJIMA
        IEEE TRANSACTIONS ON COMPUTERS, Sep. 1991, Peer-reviewed
      • Log‐depth circuits for elementary functions using residue number system
        Yasuo Okabe; Naofumi Takagi; Shuzo Yajima
        Electronics and Communications in Japan (Part III: Fundamental Electronic Science), 1991, Peer-reviewed
      • An on‐line error‐detectable high‐speed array divider
        Naofumi Takagi; Shuzo Yajima
        Systems and Computers in Japan, 1991, Peer-reviewed
      • A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM EFFICIENT FOR ITERATIVE MODULAR MULTIPLICATIONS
        N TAKAGI
        10TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, 1991, Peer-reviewed
      • ARITHMETIC UNIT BASED ON A HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDITION TREE
        N TAKAGI
        ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS II, 1991, Peer-reviewed
      • A Memory-Type Parallel Computation Model and Its Computational Power - Yet Another Approach to Supercomputing
        TAKAGI Naofumi; TAKENAGA Yasuhiko; YAJIMA Shuzo
        Transactions of IPSJ, Nov. 1990, Peer-reviewed
      • Log Depth Circuits for Elementary Functions Using Residue Number System
        OKABE Yasuo; TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IEICE, Sep. 1990, Peer-reviewed
      • An On-Line Error Detectable High-Speed Array Divider
        TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IEICE, Feb. 1990, Peer-reviewed
      • Vector Algorithms for Generating Prime Implicants of Logic Functions Based on Consensus Expansion
        OCHI Hiroyuki; TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IEICE, Sep. 1989, Peer-reviewed
      • On-line error-detectable array divider with a redundant binary representation and a residue code.
        Naofumi Takagi; Shuzo Yajima
        Digest of Papers - FTCS (Fault-Tolerant Computing Symposium), Oct. 1988, Peer-reviewed
      • Sorting on a Vector Processor
        ISHIURA Nagisa; TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IPSJ, Apr. 1988, Peer-reviewed
      • Vector Algorithms for Generating Prime Implicants of Logic Functions
        TAKAGI Naofumi; OCHI Hiroyuki; YAJIMA Shuzo
        Proceedings - Third International Conference on Supercomputing, 1988, Peer-reviewed
      • ONLINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER USING REDUNDANT BINARY REPRESENTATION AND 3-RAIL LOGIC
        N TAKAGI; S YAJIMA
        IEEE TRANSACTIONS ON COMPUTERS, Nov. 1987, Peer-reviewed
      • A Hardware-Oriented Unification Algorithm Using a Cotent Addressable Memory
        OHKUBO Masaaki; YASUURA Hiroto; TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IPSJ, Sep. 1987, Peer-reviewed
      • DESIGN OF HIGH SPEED MOS MULTIPLIER AND DIVIDER USING REDUNDANT BINARY REPRESENTATION.
        Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi
        Proceedings - Symposium on Computer Arithmetic, May 1987, Peer-reviewed
      • ON HIGH-SPEED PARALLEL ALGORITHMS USING REDUNDANT CODING.
        Hiroto Yasuura; Naofumi Takagi; Shuzo Tajima
        Systems and Computers in Japan, Mar. 1987, Peer-reviewed
      • A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE
        Y HARATA; Y NAKAMURA; H NAGASE; M TAKIGAWA; N TAKAGI
        IEEE JOURNAL OF SOLID-STATE CIRCUITS, Feb. 1987, Peer-reviewed
      • On high‐speed parallel algorithms using redundant coding
        Hiroto Yasuura; Naofumi Takagi; Shuzo Yajima
        Systems and Computers in Japan, 1987, Peer-reviewed
      • A Hardware Algorithm for Computing Sine and Cosine Using Redundant Binary Representation
        TAKAGI Naofumi; ASADA Tohru; YAJIMA Shuzo
        Transactions of IECE, Jun. 1986, Peer-reviewed
      • A square root hardware algorithm using redundant binary representation
        Naofumi Takagi; Shuzo Yajima
        Systems and Computers in Japan, 1986, Peer-reviewed
      • Hardware Algorithms for Computing Expornentials and Logarithms Using Redundant Binary Representation
        TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IECE, Jan. 1986, Peer-reviewed
      • A Square Root Hardware Algorithm Using Redundant Binary Representation
        TAKAGI Naofumi; YAJIMA Shuzo
        Transactions of IECE, Jan. 1986, Peer-reviewed
      • ON-LINE ERROR-DETECTABLE HIGH-SPEED MULTIPLIER WITH A REDUNDANT BINARY ADDER TREE.
        Naofumi Takagi; Shuzo Yajima
        Proceedings - IEEE International Symposium on Circuits and Systems, 1985, Peer-reviewed
      • HIGH-SPEED VLSI MULTIPLICATION ALGORITHM WITH A REDUNDANT BINARY ADDITION TREE
        N TAKAGI; H YASUURA; S YAJIMA
        IEEE TRANSACTIONS ON COMPUTERS, 1985, Peer-reviewed
      • A HARDWARE SORT-MERGE SYSTEM
        N TAKAGI; CK WONG
        IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1985, Peer-reviewed
      • High Speed Multiplier Using Redundant Binary Adder Tree
        HARATA Yoshihisa; NAKAMURA Yoshio; NAGASE Hiroshi; TAKIGAWA Mitsuharu; TAKAGI Naofumi
        Proceedings - IEEE International Conference on Computer Design 1984 (ICCD'84), Oct. 1984, Peer-reviewed
      • An Implementation and Evaluation of the Parallell Enumeration Sorting Circuit
        TAKAGI Naofumi; YASUURA Hiroto; TAIMA Kenji; HAYATA Hiroshi; YAJIMA Shuzo
        Transactions of IECE, May 1984, Peer-reviewed
      • A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation
        TAKAGI Naofumi; YASUURA Hiroto; YAJIMA SHUZO
        Transactions of IECE, Apr. 1984, Peer-reviewed
      • A VLSI-Oriented High-Speed Multiplier Using a Redandant Binary Addition Tree
        TAKAGI Naofumi; YASUURA Hiroto; YAJIMA Shuzo
        Transaction of IECE, Jun. 1983, Peer-reviewed
      • VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE.
        Naofumi Takagi; Hiroto Yasuura; Shuzo Yajima
        Systems, computers, controls, 1983, Peer-reviewed
      • A High-Speed Sorting Circuit Using Parallel Enumeration Sort
        YASUURA Hiroto; TAKAGI Naofumi
        Transactions of IECE, Feb. 1982, Peer-reviewed
      • THE PARALLEL ENUMERATION SORTING SCHEME FOR VLSI
        H YASUURA; N TAKAGI; S YAJIMA
        IEEE TRANSACTIONS ON COMPUTERS, 1982, Peer-reviewed

      Misc.

      • mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices
        Hideki Takase; Tomoya Mori; Kazuyoshi Takagi; Naofumi Takagi
        情報処理学会論文誌, 15 Feb. 2020
      • ROSベースの自律移動ロボットにおけるFPGA統合開発プラットフォーム (VLSI設計技術)
        田村 爽; 新田 泰大; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 30 Jan. 2019
      • (m, k)-firm制約下の弱ハードリアルタイムシステムにおける動的電圧周波数制御 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2018)
        水野 有美; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • AUTOSARカーネルにおけるターゲット依存記述のバージョン更新自動化手法 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2018)
        廣瀬 秀樹; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • ROSノード軽量実行環境mROSにおけるデバイス内のノード間通信手法 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2018)
        森 智也; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • (m, k)-firm制約下の弱ハードリアルタイムシステムにおける動的電圧周波数制御 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2018)
        水野 有美; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • AUTOSARカーネルにおけるターゲット依存記述のバージョン更新自動化手法 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2018)
        廣瀬 秀樹; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • ROSノード軽量実行環境mROSにおけるデバイス内のノード間通信手法 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2018)
        森 智也; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 07 Mar. 2018
      • mROS : 組込みデバイス向けROSノード軽量実行環境 (ディペンダブルコンピューティング) -- (デザインガイア2017 : VLSI設計の新しい大地)
        森 智也; 高瀬 英希; 高本 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 06 Nov. 2017
      • A light-weight runtime environment for ROS components using the embedded device
        森 智也; 高瀬 英希; 高木 一義; 高木 直史
        組込みシステムシンポジウム2017論文集, 17 Aug. 2017
      • Implementation of SLAM on Programmable SoCs for the Autonomous Robot
        森 智也; 高瀬 英希; 高木 一義; 高木 直史
        システム制御情報学会研究発表講演会講演論文集, 25 May 2016
      • On-chip Implementation of Random-Access-Memory and RSFQ Microprocessor with High-Functionality
        佐藤 諒; 安藤 友紀; 田中 雅光; 藤巻 朗; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 20 Apr. 2016
      • A Comparative Evaluation of SW/HW Communication Methods on System Design Environments for Programmable SoCs
        谷 祐輔; 高瀬 英希; 大川 猛; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 24 Mar. 2016
      • An Evaluation Environment of Power Management for Single-ISA Heterogeneous Multi-core Systems
        青野 和巳; 高瀬 英希; 松原 豊; 高木 一義; 高木 直史
        組込みシステムシンポジウム2015論文集, 14 Oct. 2015
      • All Five-Variable Logic Functions Can Be Computed by Three-Input Majority Gates with Depth Four
        Moriya Masao; Takagi Kazuyoshi; Takagi Naofumi
        RIMS Kokyuroku, Apr. 2015
      • 行列多項式$I+A+A^2+\dots+A^{N-1}$の計算における行列乗算回数 (計算理論とアルゴリズムの新潮流)
        松本 耕太朗; 高木 直史; 高木 一義
        数理解析研究所講究録, Apr. 2015
      • 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (コンピュータシステム)
        岩田 淳; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 06 Mar. 2015
      • 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング (ディペンダブルコンピューティング)
        岩田 淳; 高瀬 英希; 高木 一義; 高木 直史
        電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 06 Mar. 2015
      • Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication
        鬼頭 信貴; 秋元 一志; 高木 直史
        研究報告組込みシステム(EMB), 27 Feb. 2015
      • 同一命令セットヘテロジニアスマルチコアのための消費エネルギーを削減するタスクスケジューリング
        岩田 淳; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムとLSIの設計技術(SLDM), 27 Feb. 2015
      • C-8-10 Design of 8-bit Serial Single-Flux-Quantum Microprocessor with Extended Functions
        Sato Ryo; Takata Kensuke; Tanaka Masamitsu; Fujimaki Akira; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the IEICE General Conference, 24 Feb. 2015
      • C-8-8 A Placement and Routing Method for Optimizing Pulse Arrival Timing of Single-Flux-Quantum Circuits
        Nishimura Sho; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the IEICE General Conference, 24 Feb. 2015
      • An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
        YATAKA Hiroyuki; TAKAGI Naofumi; TAKAGI Kazuyoshi
        IEICE technical report. Computer systems, 26 Nov. 2014
      • A complex multiplier using two floating-point fused multiply-add unit
        TAKATA Yuhei; TAKAGI Naofumi; TAKAGI Kazuyoshi
        IEICE technical report. Computer systems, 26 Nov. 2014
      • A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture
        IWATA ATSUSHI; TAKASE HIDEKI; TAKAGI KAZUYOSHI; TAKAGI NAOFUMI
        IEICE technical report. Dependable computing, 26 Nov. 2014
      • A Task Migration Method for Real-time Systems on Heterogeneous Multi-Cores with Single Instruction Set Architecture
        岩田 淳; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムとLSIの設計技術(SLDM), 19 Nov. 2014
      • C-8-7 A Method to Search Minimum Level Circuits for Logic Functions Using Three-Input Majority Gates
        Moriya Masao; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the Society Conference of IEICE, 09 Sep. 2014
      • C-8-10 Demonstration of the 4-bit Parallel Bit-Slice High-Throughput ALU
        Takata Kensuke; Tanaka Masamitsu; Fujimaki Akira; Tanaka Kang-Ming; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the Society Conference of IEICE, 09 Sep. 2014
      • C-8-9 Design Method of Dual-Rail SFQ Logic Circuits Using RSBDD and BDD
        Ando Yuki; Takagi Kazuyoshi; Takagi Naofumi; Yamashita Shigeru
        Proceedings of the Society Conference of IEICE, 09 Sep. 2014
      • C-8-12 Design of Bit-Sliced Register File for 32-bit Single-Flux-Quantum Microprocessors
        Tanaka Masamitsu; Takata Kensuke; Takagi Kazuyoshi; Takagi Naofumi; Fujimaki Akira
        Proceedings of the Society Conference of IEICE, 09 Sep. 2014
      • On the number of matrix multiplications in the evaluation of the matrix polynomial I+A+A^2+…+A^
        MATSUMOTO Kotaro; TAKAGI Naofumi; TAKAGI Kazuyoshi
        IEICE technical report. Theoretical foundations of Computing, 02 Sep. 2014
      • Design and Evaluation of the 4-bit Parallel Bit-Slice-ALU
        TAKATA Kensuke; TANAKA Masamitsu; FUJIMAKI Akira; TANG Kang-Ming; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Technical report of IEICE. SCE, 23 Jul. 2014
      • Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication
        KITO Nobutaka; AKIMOTO Kazushi; TAKAGI Naofumi
        IEICE technical report. Dependable computing, 20 Jun. 2014
      • Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC
        東 遼平; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムLSI設計技術(SLDM), 08 Mar. 2014
      • Implementation of a Front-End and Case Study of the System Design Environment for Programmable SoC
        AZUMA RYOHEI; TAKASE HIDEKI; TAKAGI KAZUYOSHI; TAKAGI NAOFUMI
        IEICE technical report. Computer systems, 08 Mar. 2014
      • An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality
        AONO KAZUMI; IWATA ATSUSHI; TAKASE HIDEKI; TAKAGI KAZUYOSHI; TAKAGI NAOFUMI
        IEICE technical report. Dependable computing, 08 Mar. 2014
      • C-8-6 Design and Implementation of Bit-Slice Barrel Shifter for 32-bit Single-Flux-Quantum Microprocessors
        Tanaka Masamitsu; Ohmomo Yukio; Takagi Kazuyoshi; Takagi Naofumi; Fujimaki Akira
        Proceedings of the IEICE General Conference, 04 Mar. 2014
      • A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs
        東遼平; 高瀬英希; 高木一義; 高木直史
        研究報告システムLSI設計技術(SLDM), 21 Jan. 2014
      • A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs
        東 遼平; 高瀬 英希; 高木 一義; 高木 直史
        Technical report of IEICE. VLD, 21 Jan. 2014
      • A VLSI algorithm for computing correctly rounded hypotenuse
        YATAKA Hiroyuki; TAKAGI Naofumi
        IEICE technical report. Dependable computing, 27 Nov. 2013
      • Estimation for Method of Controller Implementation in High-Level Synthesis
        須田 瑛大; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムLSI設計技術(SLDM), 20 Nov. 2013
      • Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis
        SUDA AKIHIRO; TAKASE HIDEKI; TAKAGI KAZUYOSHI; TAKAGI NAOFUMI
        Technical report of IEICE. VLD, 20 Nov. 2013
      • Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis
        須田 瑛大; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムLSI設計技術(SLDM), 20 Nov. 2013
      • High-Speed Demonstration of an SFQ Half-Precision Floating-Point Adder using the 10kA/cmz Nb Process
        Kato Taiichi; Yamanashi Yuki; Yoshikawa Nobuyuki; Fujimaki Akira; Takagi Naofumi; Takagi Kazuyoshi; Nagasawa Shuichi
        Proceedings of the Society Conference of IEICE, 03 Sep. 2013
      • C-003 Implementations and Comparative Evaluation of DVFS algorithm on the Embedded RTOS
        Iwata Atsushi; Takase Hideki; Takagi Kazuyoshi; Takagi Naofumi
        情報科学技術フォーラム講演論文集, 20 Aug. 2013
      • Multiplier with concurrent error detection by partial duplication
        AKIMOTO Kazushi; KITO Nobutaka; TAKAGI Naofumi
        IEICE technical report. Dependable computing, 13 Mar. 2013
      • Self-Checking Carry Look-ahead Adder by Carry-bit Duplication
        MITOMA Akihiro; KITO Nobutaka; TAKAGI Naofumi
        IEICE technical report. Dependable computing, 13 Mar. 2013
      • Multiplier with concurrent error detection by particial duplication
        秋元 一志; 鬼頭 信貴; 高木 直史
        研究報告システムLSI設計技術(SLDM), 06 Mar. 2013
      • Multiplier with concurrent error detection by particial duplication
        秋元 一志; 鬼頭 信貴; 高木 直史
        研究報告組込みシステム(EMB), 06 Mar. 2013
      • Threading Method for Polyhedral Optimization in High Level Synthesis
        SUDA AKIHIRO; TAKASE HIDEKI; TAKAGI KAZUYOSHI; TAKAGI NAOFUMI
        IEICE technical report. Computer systems, 06 Mar. 2013
      • Evaluation Environment for Configuration of Floating-Point Unit Arrays
        ITOH Yuya; TAKASE Hideki; TAKAGI Kazuyoshi; TAKAGI Naofumi
        IEICE technical report. Computer systems, 06 Mar. 2013
      • Threading Method for Polyhedral Optimization in High Level Synthesis
        須田 瑛大; 高瀬 英希; 高木 一義; 高木 直史
        研究報告組込みシステム(EMB), 06 Mar. 2013
      • Evaluation Environment for Configuration of Floating-Point Unit Arrays
        伊藤 勇也; 高瀬 英希; 高木 一義; 高木 直史
        研究報告組込みシステム(EMB), 06 Mar. 2013
      • C-8-3 Evaluation of 8-bit Parallel Adder Designed Using Timing-Driven Automatic Routerfor Multi-Layered Single-Flux-Quantum Circuits
        Tanaka Masamitsu; Takeshima Shota; Takagi Kazuyoshi; Takagi Naofumi; Fujimaki Akira
        Proceedings of the IEICE General Conference, 05 Mar. 2013
      • C-8-4 High-Speed Test of an SFQ Half-Precision Floating-Point Adder using the 10kA/cm^2 Nb Process
        Kato Taiichi; Yoshikawa Nobuyuki; Fujimaki Akira; Takagi Naofumi; Takagi Kazuyoshi; Nagasawa Shuichi
        Proceedings of the IEICE General Conference, 05 Mar. 2013
      • C-8-23 A Logic Gate Placement Method for Single-Flux-Quantum Circuits
        Nishimura Sho; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the IEICE General Conference, 05 Mar. 2013
      • A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication
        KITO Nobutaka; TAKAGI Naofumi
        IEICE technical report. Dependable computing, 19 Nov. 2012
      • A Speculative Execution Method for Indefinite Loops in High Level Synthesis
        荒木 達真; 高瀬 英希; 高木 一義; 高木 直史
        研究報告システムLSI設計技術(SLDM), 19 Nov. 2012
      • A Speculative Execution Method for Indefinite Loops in High Level Synthesis
        ARAKI Tatuma; TAKASE Hideki; TAKAGI Kazuyosi; TAKAGI Naohumi
        IEICE technical report. Dependable computing, 19 Nov. 2012
      • C-8-14 Demonstration of SFQ Half-Precision Floating-Point Multiplier using 10 kA/cm^2 Nb Process
        Peng Xizhu; Shimamura Yasuhiro; Yamanashi Yuki; Yoshikawa Nobuyuki; Fujimaki Akira; Takagi Kazuyoshi; Takagi Naofumi; Nagasawa Shuichi
        Proceedings of the Society Conference of IEICE, 28 Aug. 2012
      • C-8-13 Measurement and Test of an SFQ half-precision floating-point adder using the 10 kA/cm^2 Nb process
        Kato Taiichi; Hinago Kazuya; Yoshikawa Nobuyuki; Fujimaki Akira; Takagi Kazuyoshi; Takagi Naofumi; Nagasawa Shuichi
        Proceedings of the Society Conference of IEICE, 28 Aug. 2012
      • C-8-11 A Method for Timing Analysis of Synchronous-Clocking Single-Flux-Quantum Circuit
        KAWAGUCHI Takahiro; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Proceedings of the Society Conference of IEICE, 28 Aug. 2012
      • SFQ Bit-Slice Floating Point Adder
        OHMOMO Yukio; NARUSE Yohei; KITO Nobutaka; TAKAGI Naofumi; TAKAGI Kazuyoshi
        Technical report of IEICE. SCE, 12 Jul. 2012
      • Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits
        NARUSE Yohei; KITO Nobutaka; TAKAGI Naofumi
        Technical report of IEICE. SCE, 12 Jul. 2012
      • C-8-14 Circuit Partitioning Method for Routing of SFQ circuits
        Naruse Yohei; Kito Nobutaka; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the IEICE General Conference, 06 Mar. 2012
      • A-3-5 Loop Parallelization Exploiting Array Access Ordering in High-Level Synthesis
        Ohno Shinji; Takagi Kazuyoshi; Takagi Naofumi
        Proceedings of the IEICE General Conference, 06 Mar. 2012
      • Equivalence checking method of timed logic formulae for verification of sinde-flux-quantum circuit
        KAWAGUCHI Takahiro; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Technical report of IEICE. VLD, 28 Feb. 2012
      • CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis
        OHNO Shinji; TAKAGI Kazuyoshi; TAKAGI Naofumi
        Technical report of IEICE. VLD, 28 Feb. 2012
      • Nbアドバンストプロセスを用いた単一磁束量子浮動小数点演算器の設計
        貝沼世樹; 島村泰浩; 宮岡史滋; 山梨裕希; 吉川信行; 藤巻朗; 高木直史; 高木一義
        電子情報通信学会超伝導エレクトロニクス研究会SCE2009-19, 20 Oct. 2009
      • 再構成可能なデータパスに向けた単一磁束量浮動小数点除算器の実証
        田中雅光; 小畑幸嗣; 高木一義; 高木直史; 吉川信行
        電子情報通信学会超伝導エレクロトニクス研究会SCE2008-27, Oct. 2008
      • SFQ半精度浮動小数点乗算器の設計と試作
        原浩史; 小畑幸嗣; 朴熙中; 山梨裕希; 武富一博; 吉川信行; 田中雅光; 伊藤祐喜; 藤巻朗; 高木直史; 高木一義
        電子情報通信学会超伝導エレクロトニクス研究会SCE2007-32, Jan. 2008
      • A Desk-Side Supercomputer with RSFQ Reconfigurable Data-Paths
        N. Takagi; K.Murakami; A. Fujimaki; N. Yoshikawa; K. Inoue; H. Honda
        日本学術振興会 超伝導エレクトロニクス第146委員会 創立25周年記念シンポジウム, Oct. 2007
      • 単一磁束量子回路による再構成可能な大規模データパスをもつプロセッサ
        高木直史; 村上和彰; 藤巻朗; 井上弘士; 本田宏明; 吉川信行
        電子情報通信学会超伝導エレクロトニクス研究会SCE2006-36、東京, Jan. 2007
      • BDDに基づくSFQ論理回路の新しい実現方法
        西海尚伸; 伊藤真紀; 吉川信行; 小畑幸嗣; 高木一義; 高木直史
        電子情報通信学会超伝導エレクトロニクス研究会, Oct. 2004
      • Multiple-valued-digit number representations in arithmetic circuit algorithms
        N Takagi
        ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2002, Peer-reviewed, Invited

      Presentations

      • Development of CAD tools for SFQ logic circuits and design of data-path circuits for SFQ bit-slice processors
        TAKAGI Naofumi
        The 10th Superconducting SFQ VLSI Workshop (SSV 2017), 20 Feb. 2017
      • Research Results of CREST-JST SFQ-RDP Project and Future Issues
        TAKAGI Naofumi
        The 6th Superconducting SFQ VLSI Workshop (SSV 2013), 22 Nov. 2013, JST-ALCA SFQ Project and MEXT SFQ Project
      • An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits
        TAKAGI Naofumi
        24th International Symposium on Superconductivity, 26 Oct. 2011, International Superconductivity Technology Center (ISTEC)

      Books and Other Publications

      • New Inter-University Logic Circuits
        TAKAGI Naofumi; ISO Naoyuki, Contributor, Chapters 0-8
        Ohmsha, Dec. 2010, Not refereed
      • VLSI Algorithms for Arithmetic Operations
        TAKAGI Naofumi, Single work
        Corona Publishing Co., LTD, Mar. 2005, Not refereed
      • The VLSI Handbook
        CHEN Waikai Ed; MUROGA Saburo; TAKAGI Naofumi, Joint work, Chapters 38-40
        CRC Press (with IEEE Press), 2000, Not refereed
      • Inter-University Logic Circuits and Automata
        INAGAKI Yasuyoshi; TAKAGI Naofumi; HAYASHI Terumine; NAOI Tohru, Contributor, Chapters 1-4, Chapter 6 Sections 4-5
        Ohmsha, Jan. 1998, Not refereed
      • Logic Circuits
        TAKAGI Naofumi, Single work
        Shokodo, Apr. 1997, Not refereed
      • Experiments in Information Engineering
        IKEDA Katsuo; SHIBAYAMA Kiyoshi; TAKAGI Naofumi, Contributor, Chapter 6: Logic Elements
        オーム社, Mar. 1993, Not refereed

      Industrial Property Rights

      • 並列係数ソーティング回路
      • Arithmetic processor and multiplier using redundant signed digit arithmetic
      • Arithmetic processor and divider using redundant signed digit
      • Adder circuitry utilizing redundant signed digit operands
      • High speed multiplier utilizing signed-digit and carry-save operands
      • Arithmetic processor using singed-digit representation of internal operands
      • Arithmetic processor using signed-digit representation of external operands
      • 演算処理装置
      • 演算処理装置
      • 演算処理装置
      • 演算処理装置
      • 演算処理装置
      • 演算処理装置
      • 演算処理装置
      • 加算装置
      • Method and hardware for computing reciprocal square root and program for the same
      • 平方根の逆数計算方法、計算回路、及びプログラム
      • 剰余系の計算方法及び装置並びにプログラム
      • 再構成可能データパスプロセッサ
      • 剰余系の計算方法及び装置
      • Arithmetic processor and multiplier using redundant signed digit arithmetic
      • Arithmetic processor and divider using redundant signed digit
      • Adder circuitry utilizing redundant signed digit operands
      • High speed multiplier utilizing signed-digit and carry-save operands
      • Arithmetic processor using singed-digit representation of internal operands
      • Arithmetic processor using signed-digit representation of external operands
      • Method and hardware for computing reciprocal square root and program for the same

      Works

      • 単一磁束量子回路による再構成可能な低電力高性能プロセッサ
        From 2006, To 2011
      • Low-power, high-performance, reconfigurable processor using single flux quantum circuits
        From 2006, To 2011
      • テスト容易な演算回路の自動合成に関する研究
        From 2008
      • ハードウェアアルゴリズムの性能評価に関する研究
        From 2004, To 2007
      • SFQ回路高速化アーキテクチャの研究
        From 2002, To 2006
      • Research on architecture of high-speed SFQ circuits
        From 2002, To 2006
      • 有限体上の諸演算のためのハードウェアアルゴリズムに関する研究
        From 2002, To 2004
      • Researches on hardware algorithms for arithmetic operations in finite fields
        From 2002, To 2004
      • 高速算術演算回路の研究
        From 2000, To 2002
      • 高機能演算回路のためのハードウェアアルゴリズムに関する研究
        From 1998, To 2000
      • Srudies on hardware algorithms for high-performance arithmetic circuits
        From 1998, To 2000
      • 高速ディジタル信号処理のための複合算術演算回路に関する研究
        From 1996, To 1997
      • Studies on combined arithmetic circuits for high-speed digital signal processing
        From 1996, To 1997

      Awards

      • Sep. 2005
        Organizing Committee of CHES2005, Best Paper Award of 7th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005)
      • Apr. 2005
        文部科学省, 平成17年度科学技術分野の文部科学大臣表彰 研究部門
      • Nov. 1995
        日本アイ・ビー・エム, 第9回 日本IBM科学賞
      • May 1995
        情報処理学会, 情報処理学会 第3回(平成6年度)坂井記念特別賞
      • Mar. 1994
        電気通信普及財団, 第9回 電気通信普及財団 テレコムシステム技術賞 奨励賞
      • Mar. 1991
        電子情報通信学会, 電子情報通信学会 第6回(平成2年度)篠原記念学術奨励賞
      • May 1989
        情報処理学会, 情報処理学会 1988年度論文賞
      • May 1988
        電子情報通信学会, 電子情報通信学会 1987年度論文賞
      • Nov. 1984
        Organizing Committee of ICCD'84, Outstanding Paper Award of IEEE International Conference on Computer Design (ICCD'84)
      • Apr. 2014
        IEEE Computer Society 2014/04/, Meritorious Service Certificate
      • Apr. 2017
        ACM , Service Award
      • Sep. 2017
        電子情報通信学会 基礎・境界ソサイエティ, 功労賞

      External funds: Kakenhi

      • Research on Ultra-Low-Power Sub-terahertz Superconductor Quantum Digital Systems Based on Pulse-Driven Circuit Technology
        Grant-in-Aid for Specially Promoted Research
        Science and Engineering
        Nagoya University
        藤巻 朗
        From 23 Apr. 2018, To 31 Mar. 2023, Granted
        単一磁束量子回路;半磁束量子;磁性ジョセフソン接合;単一磁束量子;パルス論理;π接合;半磁束量子回路;パルス駆動回路;磁束量子回路;超伝導回路
      • Studies on hardware assist of floating point function calculation
        Grant-in-Aid for Scientific Research (B)
        Kyoto University
        Naofumi Takagi
        From 01 Apr. 2016, To 31 Mar. 2020, Project Closed
        計算機システム;関数計算;浮動小数点演算;FPGA;逆三角関数;FPGA;指数・対数関数計算;正弦・余弦関数計算
      • Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
        Grant-in-Aid for Scientific Research (B)
        Kyoto University
        Naofumi TAKAGI
        From 01 Apr. 2012, To 31 Mar. 2015, Project Closed
        算術演算回路;演算器アレイ;オンライン誤り検出;(2)算術演算回路
      • Research on synthesis of easily-testable arithmetic circuits
        Grant-in-Aid for Scientific Research (B)
        Nagoya University
        Naofumi TAKAGI
        Project Closed
        VLSIのテスト;算術演算回路;乗算器;加算器;テスト容易化設計
      • Studies on Logic Design and Design Automation of Single-Flux-Quantum Circuits based on Localized Electromagnetic Waves
        Grant-in-Aid for Scientific Research on Priority Areas
        Science and Engineering
        Nagoya University
        Takagi KAZUYOSHI;Kazuyoshi TAKAGI
        Project Closed
        単一磁束量子回路;局在電磁波配線;論理設計支援;クロック配信;タイミング検証;単一磁束量子論理回路
      • ハードウェアアルゴリズムの性能評価に関する研究
        Grant-in-Aid for Scientific Research on Priority Areas
        Science and Engineering
        Nagoya University
        高木 直史
        Project Closed
        アルゴリズム;ハードウェアアルゴリズム;算術演算回路;組合せ回路;VLSI;計算複雑さ
      • Researches on hardware algorithms for arithmetic operations in finite fields.
        Grant-in-Aid for Scientific Research (B)
        Nagoya University
        Naofumi TAKAGI
        Project Closed
        有限体上の演算;剰余系演算;整数除算;剰余計算;暗号処理;ハードウェアアルゴリズム;VLSI;乗算剰余算;剰余系除算;有限体上の除算;暗号化・復号, finite field arithmetic;modular arithmetic;integer Division;modular reduction;cryptosystem;hardware algorithm;VLSI
      • Studies on hardware algorithms for high-performance arithmetic circuits
        Grant-in-Aid for Scientific Research (C)
        Nagoya University
        Naofumi TAKAGI
        Project Closed
        算術演算;ハート・ウェアアルゴリズム;VLSI;ユークリッドノルム計算;立方根計算;べき乗算;GF(2^m)上の除算;剰余除算;ハードウェアアルゴリズム;ノルム計算;コンピュータグラフィクス;符号化;復号;三角関数計算;加算;加算木;乗算, arithmetic circuit;hardware algorithm;VLSI;Euclidean norm computation;cube rooting;powering;division in GF (2^m);modular division
      • Studies on combined arithmetic circuits for high-speed digital signal processing
        Grant-in-Aid for Scientific Research (C)
        Nagoya University
        Naofumi TAKAGI
        Project Closed
        算術演算;乗算;除算;開平;積和演算;べき乗算;剰余除算;ハードウェアアルゴリズム;べき乗計算;ディジタル信号処理, Computer arithmetic;Multiplication;Division;Square rooting;Multiply-addition;Powering;Modular division;Hardware algorithm
      • 剰余系演算用高速アルゴリズムに関する研究
        Grant-in-Aid for Encouragement of Young Scientists (A)
        Nagoya University
        高木 直史
        Project Closed
        剰余系演算;剰余乗算;剰余べき乗算;剰余除算;アルゴリズム;ハードウェアアルゴリズム;計算複雑さ
      • 論理回路のレイアウト複雑さに関する研究
        Grant-in-Aid for Encouragement of Young Scientists (A)
        Nagoya University
        高木 直史
        Project Closed
        レイアウト;計算複雑さ;VLSI;乗算器;線形配置問題
      • 冗長表現を用いた高速演算回路の自動合成に関する研究
        Grant-in-Aid for Encouragement of Young Scientists (A)
        Kyoto University
        高木 直史
        Project Closed
        論理回路設計;算術演算回路;冗長表現;剰余逆数計算
      • Research on Formal Verifier of Logic Design Based on Temporal Logic
        Grant-in-Aid for Developmental Scientific Research (B)
        KYOTO UNIVERSITY
        Shuzo YAJIMA
        Project Closed
        時相論理;論理設計;形式的検証;論理関数処理;二分決定グラフ;モデルチェッキング;仕様記述;論理開数処理;形式的論理設計検証;順序回路, Temporal Logic;Logic Design;Formal Verification;Logic Function Manipulation;Binary Decision Diagram;Formal Specification;Model Checking
      • Basic Research on High-Speed Boolean Function Manipulator
        Grant-in-Aid for General Scientific Research (B)
        KYOTO UNIVERSITY
        Shuzo YAJIMA
        Project Closed
        論理関数;二分決定グラフ;論理関数処理;論理設計支援;並列アルゴリズム;計算複雑さ;内容アドレスメモリ;組合せ問題;形式的設計検証, Boolean Function;Binary Decision Diagram;Boolean Function Manipulation;Computer Aided Logic Design;Prallel Algorithm;Computational Complexity;Content Addressable Memory;Combinatorial Problem
      • Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
        Grant-in-Aid for Developmental Scientific Research (B)
        KYOTO UNIVERSITY
        Shuzo YAJIMA
        Project Closed
        論理合成;論理設計検証;順序回路;論理関数簡単化;状態割当て;時相論理;論理設計支援, logic synthesis;logic design verification;sequential circuits;logic function optimization;state assignment;temporal logic;computer-aided logic design
      • Research on Efficient Manipulation of Boolean Functions Using Shared Binary Decision Diagrams and Its Application to Computer Aided Logic Design
        Grant-in-Aid for General Scientific Research (B)
        Kyoto University
        Shuzo YAJIMA
        Project Closed
        論理関数;二分決定グラフ;論理関数処理;計算機援用設計;記号シミュレ-ション;タイミング検証;論理設計検証;計算複雑さ, Boolean Function;Binary Decision Diagram;Boolean Function Manipulation;computer Aided Design;Symbolic Simulation;Timing Verification;Logic Design Verification;Computational complexity
      • Research on Development of a Logic Design Verification System Based on Time-Symbolic Simulation
        Grant-in-Aid for Developmental Scientific Research (B).
        Kyoto University
        Shuzo YAJIMA
        Project Closed
        論理設計検証;タイミング検証;論理シミュレ-ション;記号シミュレ-ション;論理設計;非同期式順序回路;ハザ-ド;論立設計検証, Logic Design Verification;Timing Verification;Logic Simulation;Symbolic Simulation;Logic Design;Asynchronous Sequential Circuit;Hazard
      • Researches on Formal Logic Design Verification Based on Regular Temporal Logic
        Grant-in-Aid for General Scientific Research (C)
        Kyoto University
        Hiromi HIRAISHI
        Project Closed
        時相論理;形式的検証;論理設計;モデル検査;設計検証;仕様記述;正則集合;順序機械;共有二分決定グラフ;記号シミュレ-ション, Temporal Logic;Formal Verification;Logic Design;Model Checking
      • Researches on the Design of Highly Reliable High-Speed Arithmetic Circuits with Redundant Coding
        Grant-in-Aid for General Scientific Research (B)
        KYOTO UNIVERSITY
        Shuzo YAJIMA
        Project Closed
        算術演算回路;ハ-ドウェアアルゴリズム;耐故障設計;オンライン誤り検出;論理シミュレ-ション;故障シミュレ-ション;テスト生成;冗長符号化;ハードウェアアルゴリズム;論理シミュレーション;故障シミュレーション, Arithmetic Circuits;Hardware Algorithm;Fault-Tolerant Design;On-Line Error Detection;Logic Simulation;Fault Simulation;Test Generation;Redundant Coding
      • Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
        Grant-in-Aid for Developmental Scientific Research
        Kyoto University
        Shuzo YAJIMA
        Project Closed
        論理設計検証;論理シミュレーション;ベクトルプロセッサ;時相論理;仕様記述;ワークステーション;マルチスクリーン;論理シミュレータ;高水準ハードウェア記述;正則時相論理;代数的仕様記述, Logic Design Verification;Logic Simulation;Vector Processof;Temporal Logic;Specification Desctiption;Workstation
      • Research on Design of VLSI Oriented Hardware Algorithms Using Redundant Representation
        Grant-in-Aid for General Scientific Research (B)
        Kyoto University
        Shuzo YAJIMA
        Project Closed
        ハードウェアアルゴリズム;冗長表現;超LSI;冗長2進表現;算術演算回路;剰余数表示法;単一化操作;ハードウェア設計言語, Hardware Algorithm;Redundant Representation;VLSI; Redundant Binary Representation;Arithmetic Operation;Residue Number Representation;Unification

      External funds: others

      • Low-power, high-performance, reconfigurable processor using single-flux-quantum circuits / Development of logic design method and design autmation technologies of single-flax-quantum logic circuits
        JST-CREST
        From Oct. 2006, To 31 Mar. 2013
        高木直史
      • Superconductor Electronic System Combined with Optics and Spintronics / Development of CAD for Superconductive Digital Circuits
        JST-ALCA
        From 01 Oct. 2011, To 31 Mar. 2017
        高木直史
      list
        Last Updated :2022/05/14

        Education

        Teaching subject(s)

        • From Apr. 2011, To Mar. 2012
          Advanced Study in CCE II
          Year-long, 情報学研究科
        • From Apr. 2011, To Mar. 2012
          通信情報システム特別研究1
          Year-long, 情報学研究科
        • From Apr. 2011, To Mar. 2012
          通信情報システム特別研究2
          Year-long, 情報学研究科
        • From Apr. 2011, To Mar. 2012
          Advanced Study in CCE I
          Year-long, 情報学研究科
        • From Apr. 2011, To Mar. 2012
          計算機アーキテクチャ1(計算機)
          Fall, 工学部
        • From Apr. 2011, To Mar. 2012
          計算機アーキテクチャ2(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          論理回路(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          情報と職業
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究1(16年以降入学者)(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究1(16年以降入学者)(計算機)
          Fall, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究2(16年以降入学者)(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究2(16年以降入学者)(計算機)
          Fall, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究1(15年以前入学者)(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究1(15年以前入学者)(計算機)
          Fall, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究2(15年以前入学者)(計算機)
          Spring, 工学部
        • From Apr. 2011, To Mar. 2012
          特別研究2(15年以前入学者)(計算機)
          Fall, 工学部
        • From Apr. 2011, To Mar. 2012
          並列計算機アーキテクチャ
          Spring, 情報学研究科
        • From Apr. 2011, To Mar. 2012
          ハードウェアアリゴリズム
          Fall, 情報学研究科
        • From Apr. 2012, To Mar. 2013
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2012, To Mar. 2013
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2012, To Mar. 2013
          Computer Architecture 1
          Fall, 工学部
        • From Apr. 2012, To Mar. 2013
          Computer Architecture 2
          Spring, 工学部
        • From Apr. 2012, To Mar. 2013
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2012, To Mar. 2013
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2012, To Mar. 2013
          Logic Circuits
          Spring, 工学部
        • From Apr. 2012, To Mar. 2013
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2012, To Mar. 2013
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2013, To Mar. 2014
          Computer Architecture 1
          Fall, 工学部
        • From Apr. 2013, To Mar. 2014
          Computer Architecture 2
          Spring, 工学部
        • From Apr. 2013, To Mar. 2014
          Logic Circuits
          Spring, 工学部
        • From Apr. 2013, To Mar. 2014
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2013, To Mar. 2014
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2013, To Mar. 2014
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2013, To Mar. 2014
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Computer Architecture 1
          Fall, 工学部
        • From Apr. 2014, To Mar. 2015
          Computer Architecture 2
          Spring, 工学部
        • From Apr. 2014, To Mar. 2015
          Logic Circuits
          Spring, 工学部
        • From Apr. 2014, To Mar. 2015
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2014, To Mar. 2015
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Seminar on Communications and Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Seminar on Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2014, To Mar. 2015
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2014, To Mar. 2015
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Seminar on Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Computer Architecture 1
          Fall, 工学部
        • From Apr. 2015, To Mar. 2016
          Computer Architecture 2
          Spring, 工学部
        • From Apr. 2015, To Mar. 2016
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2015, To Mar. 2016
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2015, To Mar. 2016
          Logic Circuits
          Spring, 工学部
        • From Apr. 2015, To Mar. 2016
          Seminar on Communications and Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2015, To Mar. 2016
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Seminar on Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Computer Architecture 2
          Spring, 工学部
        • From Apr. 2016, To Mar. 2017
          Computer organization
          Fall, 工学部
        • From Apr. 2016, To Mar. 2017
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2016, To Mar. 2017
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2016, To Mar. 2017
          Logical Systems
          Spring, 工学部
        • From Apr. 2016, To Mar. 2017
          Seminar on Communications and Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Advanced Study in Communications and Computer Engineering II
          Fall, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2016, To Mar. 2017
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Seminar on Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Computer organization
          Fall, 工学部
        • From Apr. 2017, To Mar. 2018
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2017, To Mar. 2018
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2017, To Mar. 2018
          Logical Systems
          Spring, 工学部
        • From Apr. 2017, To Mar. 2018
          Seminar on Communications and Computer Engineering, Advanced
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Advanced Study in Communications and Computer Engineering II
          Spring, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Advanced Study in Communications and Computer Engineering II
          Year-long, 情報学研究科
        • From Apr. 2017, To Mar. 2018
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2018, To Mar. 2019
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2018, To Mar. 2019
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2018, To Mar. 2019
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2018, To Mar. 2019
          Information and Business
          Spring, 工学部
        • From Apr. 2018, To Mar. 2019
          Graduation Thesis 1
          Spring, 工学部
        • From Apr. 2018, To Mar. 2019
          Graduation Thesis 1
          Fall, 工学部
        • From Apr. 2018, To Mar. 2019
          Graduation Thesis 2
          Spring, 工学部
        • From Apr. 2018, To Mar. 2019
          Graduation Thesis 2
          Fall, 工学部
        • From Apr. 2018, To Mar. 2019
          Computer organization
          Fall, 工学部
        • From Apr. 2018, To Mar. 2019
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2018, To Mar. 2019
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2018, To Mar. 2019
          Logical Systems
          Spring, 工学部
        • From Apr. 2019, To Mar. 2020
          Advanced Study in Communications and Computer Engineering I
          Year-long, 情報学研究科
        • From Apr. 2019, To Mar. 2020
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2019, To Mar. 2020
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2019, To Mar. 2020
          Computer organization
          Fall, 工学部
        • From Apr. 2019, To Mar. 2020
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2019, To Mar. 2020
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2019, To Mar. 2020
          Logical Systems
          Spring, 工学部
        • From Apr. 2020, To Mar. 2021
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2020, To Mar. 2021
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2020, To Mar. 2021
          Computer organization
          Fall, 工学部
        • From Apr. 2020, To Mar. 2021
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2020, To Mar. 2021
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2020, To Mar. 2021
          Logical Systems
          Spring, 工学部
        • From Apr. 2021, To Mar. 2022
          Hardware Algorithm
          Fall, 情報学研究科
        • From Apr. 2021, To Mar. 2022
          Parallel Computer Architecture
          Spring, 情報学研究科
        • From Apr. 2021, To Mar. 2022
          Computer organization
          Fall, 工学部
        • From Apr. 2021, To Mar. 2022
          Introduction to Computer Science
          Spring, 全学共通科目
        • From Apr. 2021, To Mar. 2022
          Introduction to Computer Science
          Spring, 工学部
        • From Apr. 2021, To Mar. 2022
          Logical Systems
          Spring, 工学部
        list
          Last Updated :2022/05/14

          Administration

          School management (title, position)

          • From 01 Jul. 2011, To 31 Mar. 2012
            教育用計算機専門委員会 委員
          • From 01 Oct. 2014, To 31 Mar. 2015
            京都大学情報環境整備委員会 委員
          • From 01 Oct. 2014
            教育用計算機専門委員会 委員長
          • From 01 Apr. 2015, To 30 Sep. 2016
            京都大学情報環境整備委員会 委員
          • From 01 Oct. 2014
            情報環境機構 副機構長
          • From 01 Oct. 2016, To 30 Sep. 2018
            京都大学情報環境整備委員会 委員
          • From 01 Apr. 2020, To 31 Mar. 2023
            京都大学情報環境整備委員会 委員

          Faculty management (title, position)

          • From 01 Apr. 2011, To 31 Mar. 2012
            教務委員会委員
          • From 01 Apr. 2012, To 31 Mar. 2013
            専攻長会議
          • From 01 Apr. 2012, To 31 Mar. 2013
            制規委員会委員
          • From 01 Apr. 2012, To 31 Mar. 2013
            情報セキュリティ委員会委員
          • From 01 Apr. 2013, To 31 Mar. 2014
            教務委員会委員
          • From 01 Apr. 2014, To 31 Mar. 2017
            財務委員会委員長
          • From 01 Apr. 2017, To 31 Mar. 2018
            財務委員会委員
          • From 01 Apr. 2018, To 33 Mar. 2019
            企画委員会委員
          • From 01 Apr. 2018, To 31 Mar. 2019
            情報学科長
          • From 01 Apr. 2019, To 31 Mar. 2020
            企画委員会委員
          • From 01 Apr. 2018, To 31 Mar. 2021
            工学研究科運営会議 学生・教育部門 教育担当
          • From 01 Apr. 2019, To 31 Mar. 2021
            工学部新工学教育実施専門委員会 委員
          • From 01 Apr. 2020, To 31 Mar. 2021
            教務委員会委員
          • From 01 Apr. 2021, To 31 Mar. 2022
            制規委員会委員
          • From 01 Apr. 2021, To 31 Mar. 2022
            専攻長
          • From 01 Apr. 2021, To 31 Mar. 2022
            情報セキュリティ委員会委員
          • From 01 Apr. 2020, To 31 Mar. 2022
            情報環境機構運営委員会委員
          • From 01 Apr. 2020, To 31 Mar. 2022
            情報環境機構管理委員会委員
          • From 01 Apr. 2020, To 31 Mar. 2022
            情報環境機構協議会委員
          • From 01 Apr. 2020, To 31 Mar. 2022
            情報環境機構評価委員会委員
          • From 01 Apr. 2020, To 31 Mar. 2022
            情報環境機構教育用計算機専門委員会委員長
          list
            Last Updated :2022/05/14

            Academic, Social Contribution

            Committee Memberships

            • From Oct. 2015, To Sep. 2019
              IEEE Transactions on Computers Associate Editor
            • From 2006, To 2007
              評議員, 電子情報通信学会
            • From 2005, To 2007
              評議員, 電子情報通信学会 東海支部
            • From 2004, To 2007
              委員, 電子情報通信学会 ELEX編集委員会
            • From 2007
              学生会顧問, 電子情報通信学会 東海支部
            • From 2006
              委員, 電子情報通信学会 ディペンダブルコンピューティング研究専門委員会
            • From 2003, To 2005
              評議員, 情報処理学会 東海支部
            • From 2000, To 2004
              運営委員, 情報処理学会 システムLSI設計技術研究会
            • From 1996, To 2000
              Associate Editor, IEEE Transactions on Computers
            • From 1997, To 1999
              幹事, 情報処理学会 東海支部
            • From 1994, To 1999
              委員, 電子情報通信学会 コンピュテーション研究専門委員会
            • From 1996, To 1997
              庶務幹事, 電子情報通信学会 情報・システムソサエティ運営委員会
            • From 1993, To 1996
              連絡委員, 情報処理学会 アルゴリズム研究会
            • From 1995
              Committee member, IEEE Symposium on Computer Arithmetic Steering Committee
            • From 1991, To 1994
              委員, 電子情報通信学会 学会誌編集委員会

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