Sato, Takashi(Graduate School of Informatics, Department of Informatics) | Activity Database on Education and Research, Kyoto University

Sato, Takashi

Graduate School of Informatics, Department of Informatics Professor

Last Updated :2025/04/23

Basic Information

Faculty

工学部工学部電気電子工学科

Academic Degree

工学修士(早稲田大学)

博士（情報学）(京都大学)

Last Updated :2025/04/23

Research

Research Topics, Overview of the research

Research Topics
集積システムの設計、統計的解析と最適化
Overview of the research
Physical design and optimization of integrated circuits, Reliability-aware circuit design, Variability-aware circuit design, Hardware security, Power device modeling and characterization, Emerging computing

Research Areas

Manufacturing technology (mechanical, electrical/electronic, chemical engineering), Electronic devices and equipment

Informatics, Information security

Informatics, Computer systems

Papers

Accurate oower MOSFET modeling with off-the-shelf instruments
Hajime Takayama; Yota Nishitani; Kazuki Matsumoto; Takashi Sato; Michihiro Shintani
PCIM Europe Conference, Sep. 2025

Weighted range-constrained Ising-model decoder for quantum error correction
Xinyi Guo; Hiromitsu Awano; Takashi Sato
IEEE/ACM Design Automation Conf erence (DAC), Jun. 2025, Peer-reviewed, Last author

Lookup table-based multiplication-free all-digital DNN accelerator featuring self-synchronous pipeline cccumulation
Hiroto Tagata; Takashi Sato; Hiromitsu Awano
IEEE/ACM Design Automation Conference (DAC), Jun. 2025, Peer-reviewed

A 22nm resource-frugal hyper-heterogeneous multi-modal system-on-chip towards in-orbit computing
Quan Cheng; Qiufeng Li; Weirong Dong; Mingtao Zhang; Ruilin Zhang; Mingqiang Huang; Hao Yu; Yiyu Shi; Hiromitsu Awano; Takashi Sato; Longyang Lin; Masanori Hashimoto
IEEE Custom Integrated Circuits Conference (CICC ), Apr. 2025, Peer-reviewed

GaitCloud: Leveraging spatial-temporal information for LiDAR-base gait recognition with a true-3D gait representation
Shaoxiong Zhang; Hiromitsu Awano; Takashi Sato
IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), Mar. 2025, Peer-reviewed

Test accuracy improvement of ensemble Gaussian process-based IC outlier detection using temporal similarity between wafers
Daisuke Goeda; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki; Hajime Takayama; Takashi Sato; Michihiro Shintani
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2025, Peer-reviewed

TACHI: Tests as a chip identifier
Ryosuke Sada; Michihiro Shintani; Takashi Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2025, Peer-reviewed, Last author, Corresponding author

Cryo-Compact Modeling Based on Sparse Gaussian Process
Tetsuro Iwasaki; Takashi Sato; Michihiro Shintani
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 20 Jan. 2025

Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation
Dondee Navarro; Shin Taniguchi; Chika Tanaka; Kazutoshi Kobayashi; Takashi Sato; Michihiro Shintani
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 20 Jan. 2025

Random telegraph noise observed on 65-nm bulk pMOS transistors at 3.8K
Takuma Kawakami; Takashi Sato; Hiromitsu Awano
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2025

Low voltage DNTT-based organic TFTs: layout structure, device characteristics, and its application to circuit design
Takashi Sato; Kunihiro Oshima; Zhaoxin Qin
IEEE International Display Workshop (IDW), Dec. 2024, Invited, Lead author, Corresponding author

Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir
Sosei Ikeda; Hiromitsu Awano; Takashi Sato
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, Peer-reviewed, Last author

(Invited) Redefining Outliers for On-Wafer Electrical Testing
Michihiro Shintani; Takashi Sato
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 09 Sep. 2024

BayesianSpikeFusion: accelerating spiking neural network inference via Bayesian fusion of early prediction
Takehiro Habara; Takashi Sato; Hiromitsu Awano
Frontiers in Neuroscience, 05 Aug. 2024

Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline
Hiroto Tagata; Takashi Sato; Hiromitsu Awano
IEEE Open Journal of Circuits and Systems, Sep. 2024, Peer-reviewed
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CLAPPER: Clonable LFSR-based asymmetric PUF-group with peer-to-peer equivalent response
Chen Zhenzhe; Hirofumi Shinohara; Takashi Sato
Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2024, Peer-reviewed, Last author

Triplet network-based DNA encoding for enhanced similarity image retrieval
Takefumi Koike; Hiromitsu Awano; Takashi Sato
Proc. ACM/IEEE Design Automation Conference (DAC), Jun. 2024, Peer-reviewed, Last author

SpongePUF: A modeling attack resilient strong PUF with scalable challenge response pair
Chen Zhenzhe; Takashi Sato; Hirofumi Shinohara
Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2024, Peer-reviewed, Last author

Enhancing visual similarities in DNA-based similar image retrieval
Takefumi Koike; Takashi Sato
Proc. Workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2024, Peer-reviewed, Last author

Experimental study of pass/fail threshold determination based on Gaussian process regression
Daisuke Goeda; Tomoki Nakamura; Masuo Kajiyama; Makoto Eiki; Takashi Sato; Michihiro Shintani
Proc. Workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2024, Peer-reviewed

DNA-based similar image retrieval via triplet network-driven encoder
Takefumi Koike; Hiromitsu Awano; Takashi Sato
Proc. Design, Automation and Test in Europe (DATE), Mar. 2024, Peer-reviewed, Last author

Fast parameter optimization of delayed feedback reservoir with backpropagation and gradient descent
Sosei Ikeda; Hiromitsu Awano; Takashi Sato
Proc. Design, Automation and Test in Europe (DATE), Mar. 2024, Peer-reviewed, Last author

Logic locking over TFHE for securing user data and algorithms
Kohei Suemitsu; Kotaro Matsuoka; Takashi Sato; Masanori Hashimoto
Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2024, Peer-reviewed
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Design of aging-robust clonable PUF using organic thin-film transistors and insulator-based ReRAM
Kunihiro Oshima; Kazunori Kuribara; Takashi Sato
Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2024, Peer-reviewed, Last author

HOGE: Homomorphic gates on a chip
Kotaro Matsuoka; Song Bian; Takashi Sato
Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2024, Invited, Last author

Gaussian process-based device model toward a unified current model across room to cryogenic temperatures
Michihiro Shintani; Tetsuro Iwasaki; Takashi Sato
IEEE International Conference on Microelectronic Test Structures, Apr. 2024, Peer-reviewed, Last author

Layout Design for DNTT-based Organic TFTs Considering Fringe Leakage Current
Kunihiro Oshima; Kazunori Kuribara; Takashi Sato
IEEE Journal on Flexible Electronics, 2024, Peer-reviewed, Last author

Low voltage operation of organic thin-film transistor with atmospheric coating of high-k polymer dielectric
Kazunori Kuribara; Atsushi Takei; Takashi Sato; Manabu Yoshida
Japanese Journal of Applied Physics, 15 Dec. 2023, Peer-reviewed

Low voltage operation of organic thin-film transistor with atmospheric coating of high-k polymer dielectric
Kazunori Kuribara; Atsushi Takei; Takashi Sato; Manabu Yoshida
Proc. International Conference on Solid State Devices and Materials, Sep. 2023, Peer-reviewed

Feasibility study of PLL-based analog-to-digital converter for low-voltage organic thin-film transistors
Hiroki Urabe; Kunihiro Oshima; Takashi Sato
Proc. International Conference on Solid State Devices and Materials, Sep. 2023, Peer-reviewed, Last author, Corresponding author

Uncertainty-aware haptic shared control with humanoid robots for flexible object manipulation
Takumi Hara; Takashi Sato; Tetsuya Ogata; Hiromitsu Awano
IEEE Robotics and Automation Letters, Dec. 2023, Peer-reviewed

Improving efficiency and robustness of Gaussian process based outlier detection via ensemble learning
Makoto Eiki; Tomoki Nakamura; Masuo Kajiyama; Michiko Inoue; Takashi Sato; Michihiro Shintani
Proc. International Test Conference (ITC), Oct. 2023, Peer-reviewed

Modular DFR: Digital delayed feedback reservoir model for enhancing design flexibility
Sosei Ikeda; Hiromitsu Awano; Takashi Sato
ACM Transactions on Embedded Computing Systems (TECS), Sep. 2023, Peer-reviewed, Last author

Flex-SNN: Spiking Neural Network on Flexible Substrate
Kunihiro Oshima; Kazunori Kuribara; Takashi Sato
IEEE Sensors Letters, May 2023, Peer-reviewed, Corresponding author

OPTL: Robust and area-efficient pass gate logic for organic transistors
Qin Zhaoxing; Kunihiro Oshima; Kazunori Kuribara; Takashi Sato
IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS), Jul. 2023, Peer-reviewed, Last author

Introducing transfer learning framework on device modeling by machine learning
Kota Niiyama; Hiromitu Awano; Takashi Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2023, Peer-reviewed

Aging-robust amplifier composed of p-type low voltage OTFT and organic semiconductor load
Yuto Kaneiwa; Kazunori Kuribara; Takashi Sato
Japanese Journal of Applied Physics, 09 Feb. 2023, Peer-reviewed, Last author, Corresponding author

Measurement of 64 organic thin-film transistors in an array test structure using a relay-switch board for efficient evaluation of long-term reliability
Yasuhiro Ogasahara; Kazunori Kuribara; Takashi Sato
Japanese Journal of Applied Physics, 23 Jan. 2023, Peer-reviewed, Last author

Dominant model-parameter determination for the analysis of current imbalance across paralleled power transistors
Yohei Nakamura; Michihiro Shintani; Takashi Sato
IEEE Transactions on Power Electronics, Apr. 2023, Peer-reviewed, Last author
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Special section on analog circuit techniques and related topics
Hiroki Ishikuro; Hiroyuki Ito; Takashi Sato; Takahide Sato; Hao San; Hiroo Sekiya; Nicodimus Retdian; Akira Hyogo; Yoshitaka Hirai; Yasuyuki Matsuya; Cosy Muto; Akira Yasuda; Taizo Yamawaki; Takeshi Yoshida
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Feb. 2021

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis
HAGIWARA Shiho; DATE Takanori; MASU Kazuya; SATO Takashi
IEICE Transactions on Electronics, 01 Apr. 2014

On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
SATO Takashi; ICHIMIYA Junji; ONO Nobuto; HACHIYA Koutaro; HASHIMOTO Masanori
IEICE Trans. Fundamentals, A, 01 Dec. 2005

Hardware-friendly delayed feedback reservoir for multivariate time series classification
Sosei Ikeda; Hiromitsu Awano; Takashi Sato
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Aug. 2022, Peer-reviewed, Last author

Dominant Model Parameter Extraction for Analyzing Current Imbalance in Parallel Connected SiC MOSFETs
Yohei Nakamura; Michihiro Shintani; Takashi Sato
2021 IEEE Energy Conversion Congress and Exposition (ECCE), 10 Oct. 2021

VisualNet: An end-to-end human visual system inspired framework to reduce inference latency of deep neural networks
Tianchen Wang; Jiawei Zhang; Jinjun Xiong; Song Bian; Zheyu Yan; Meiping Huang; Jian Zhuang; Takashi Sato; Yiyu Shi; Xiaowei Xu
IEEE Transactions on Computers, Jul. 2022, Peer-reviewed

Hybrid CMOS and pseudo-CMOS organic memory for flexible sensors
Zhaoxing Qin; Kazunori Kuribara; Yasuhiro Ogasahara; Takashi Sato
IEEE Sensors Journal, Mar. 2022, Peer-reviewed, Last author

Efficient analysis and mitigation of workload-dependent aging degradation
Shumpei Morita; Song Bian; Michihiro Shintani; Takashi Sato
IEEE Transactions on Computer-Aided Design (TCAD), Mar. 2022, Peer-reviewed, Last author

Investigation of layout-dependent characteristic change for improving performance of organic thin-film transistors
Kunihiro Oshima; Kazunori Kuribara; Takashi Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2022, Peer-reviewed, Last author, Corresponding author

dGPLVM: A nonparametric device model for statistical circuit simulation
Kyohei Shimozato; Takashi Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2022, Peer-reviewed, Last author, Corresponding author

Characteristic degradation of power MOSFETs by X-ray irradiation and its recovery
Masato Shiozaki; Takashi Sato
IEEE International Reliability Physics Symposium, Mar. 2022, Peer-reviewed, Last author

Adaptive outlier detection for power MOSFETs based on Gaussian process regression
Kyohei Shimozato; Michihiro Shintani; Takashi Sato
IEEE Applied Power Electronics Conference and Exposition (APEC), Mar. 2022, Peer-reviewed, Last author

Accelerating parameter extraction of power MOSFET models using automatic differentiation
Michihiro Shintani; Aoi Ueda; Takashi Sato
IEEE Transactions on Power Electronics (TPEL), Mar. 2022, Peer-reviewed, Last author

Evaluation of thermal couple impedance model of power modules for accurate die temperature estimation up to 200℃
Yohei Nakamura; Naotaka Kuroda; Ken Nakahara; Michihiro Shintani; Takashi Sato
Japanese Journal of Applied Physics (JJAP), Feb. 2022, Peer-reviewed, Last author

Respiratory rate estimation based on WiFi frame capture
Takamochi Kanda; Takashi Sato; Hiromitsu Awano; Sota Kondo; Koji Yamamoto
IEEE Consumer Communications & Networking Conference (CCNC), Jan. 2022, Peer-reviewed

Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes
Ogasahara, Yasuhiro; Kuribara, Kazunori; Oshima, Kunihiro; Qin, Zhaoxing; Sato, Takashi
Japanese Journal of Applied Physics, Dec. 2021, Peer-reviewed, Last author

Towards better standard cell library: Optimizing compound logic gates for TFHE
Kotaro Matsuoka; Yusuke Hoshizuki; Takashi Sato; Song Bian
ACM Workshop on Encrypted Computing & Applied Homomorphic Cryptography (WAHC), Nov. 2021, Peer-reviewed

APAS: Application-specific accelerators for RLWE-based homomorphic linear transformations
Song Bian; Dur E Shahwar Kundi; Kazuma Hirozawa; Weiqiang Liu; Takashi Sato
IEEE Transactions on Information Forensics & Security (TIFS), Nov. 2021, Peer-reviewed, Last author

Motion robust remote photoplethsymography via frequency domain motion artifact reduction
Suraj Hebber; Takashi Sato
IEEE Biomedical Circuits and Systems Conference (BIOCAS), Oct. 2021, Peer-reviewed, Last author

Sensitivity analysis of device parameter variation on current imbalance of parallel connected SiC power MOSFETs
Yohei Nakamura; Michihiro Shintani; Takashi Sato
IEEE Energy Conversion Congress and Expo (ECCE), Oct. 2021, Peer-reviewed, Last author

Rail-to-rail output voltage swing of inverter with organic thin-film transistor at 2.5V Vdd toward reliable operation of low leakage large scale logic circuits
Yasuhiro Ogasahara; Kazunori Kuribara; Kunihiro Oshima; Takashi Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2021, Peer-reviewed, Last author

Experimental Validation of Thermal Couple Impedance Model for Accurate Die Temperature Estimation in Power Modules
Yohei Nakamura; Naotaka Kuroda; Ken Nakahara; Michihiro Shintani; Takashi Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2021, Peer-reviewed, Last author

Statistical device modeling with arbitrary model-parameter distribution via Markov Chain Monte Carlo
Hiroki Tsukamoto; Song Bian; Takashi Sato
nternational Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 2021, Peer-reviewed, Last author, Corresponding author

Analysis of thermal concentration failure in unclamped inductive switching based on three-dimensional electro-thermal simulation with on-chip variation
Kyohei Shimozato; Yohei Nakamura; Takashi Sato
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 2021, Peer-reviewed, Last author

Virtual secure platform: A five-stage pipeline processor over TFHE
Kotaro Matsuoka; Ryotaro Banno; Naoki Matsumoto; Takashi Sato; Song Bian
Usenix Security Symposium, Aug. 2021, Peer-reviewed

Investigation of BTI-induced threshold voltage shift for power MOSFETs during switching operation
Michihiro Shintani; Takashi Sato
Proc. International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM), Jul. 2021, Peer-reviewed, Invited, Last author

Extraction of heart rate variability using commodity Wi-Fi devices
Itsuki Shirakami; Takashi Sato
IEEE Conference on Biomedical and Health Informatics (BHI), Jul. 2021, Peer-reviewed, Last author

Privacy-preserving medical image segmentation via hybrid trusted execution environment
Song Bian; Weiweng Jiang; Takashi Sato
ACM/IEEE Design Automation Conference (DAC), Jun. 2021, Peer-reviewed, Last author

An SRAM-based scratchpad memory for organic IoT sensors
Zhaoxing Qin; Kazunori Kuribara; Takashi Sato
Proc. IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS), Jun. 2021, Peer-reviewed, Last author

Automatic parallelism tuning for module learning with errors based post-quantum key exchanges on GPUs
Tatsuki Ono; Song Bian; Takashi Sato
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2021, Peer-reviewed, Last author

Clonable PUF: On the design of PUFs that share equivalent responses
Takashi Sato; Yuki Tanaka; Song Bian
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2021, Peer-reviewed, Lead author, Corresponding author

Stable organic SRAM cell with p-type access transistors
Zhaoxing Qin; Song Bian; Kazunori Kuribara; Takashi Sato
Japanese Journal of Applied Physics (JJAP), Feb. 2021, Peer-reviewed, Last author

Separation of bias stress degradation factors in organic thin-film transistors
Kunihiro Oshima; Song Bian; Kazunori Kuribara; Takashi Sato
Japanese Journal of Applied Physics (JJAP), Feb. 2021, Peer-reviewed, Last author

An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanism
Kyohei Shimozato; Yohei Nakamura; Song Bian; Takashi Sato
Japanese Journal of Applied Physics (JJAP), Feb. 2021, Peer-reviewed, Last author

Influences of device parameters variability on current sharing of parallel-connected SiC MOSFETs
Yohei Nakamura; Michihiro Shintani; Takashi Sato
Proc. IEEE Asian Test Symposium (ATS), Nov. 2020, Peer-reviewed, Last author

Measurement of BTI-induced threshold voltage shift for power MOSFETs under switching operation
Aoi Ueda; Michihiro Shintani; Michiko Inoue; Takashi Sato
Proc. IEEE Asian Test Symposium (ATS), Nov. 2020, Peer-reviewed, Invited, Last author

A Compact device model for SiC MOSFETs valid for wide-temperature range
Kohei Shimozato; Takashi Sato
Proc. IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA-Asia), Sep. 2020, Peer-reviewed, Last author, Corresponding author

An electrothermal compact model of SiC MOSFETs for simulating unclamped inductive switching tests
Kyohei Shimozato; Yohei Nakamura; Song Bian; Takashi Sato
Proc. International Conference on Solid State Devices and Materials (SSDM), Sep. 2020, Peer-reviewed

Design of an organic SRAM cell with p-type access transistors
Qin Zhaoxing; Kazunori Kuribara; Song Bian; Takashi Sato
Proc. International Conference on Solid State Devices and Materials (SSDM), Sep. 2020, Peer-reviewed, Last author

Quantification of insulator and semiconductor carrier trapping in organic thin film transistors using DNTT and TU-1
Kunihiro Oshima; Kazunori Kuribara; Song Bian; Takashi Sato
Proc. International Conference on Solid State Devices and Materials (SSDM), Sep. 2020, Peer-reviewed, Last author

BUNET: Blind medical image segmentation based on secure UNET
Song Bian; Xiaowei Xu; Weiwen Jiang; Yiyu Shi; Takashi Sato
Proc. Medical Image Computing and Computer Assisted Interventions (MICCAI), Sep. 2020, Peer-reviewed, Last author

Organic Current Mirror PUF for Improved Stability against Device Aging
Zhaoxing Qin; Michihiro Shintani; Kazunori Kuribara; Yasuhiro Ogasahara; Takashi Sato
IEEE Sensors Journal, Jul. 2020, Peer-reviewed, Last author, Corresponding author

ENSEI: Efficient Secure Inference via Frequency-domain Homomorphic Convolution for Privacy-preserving Visual Recognition
S. Bian; T. Wang; M. Hiromoto; Y. Shi; T. Sato
Computer Vision and Pattern Recognition (CVPR), Jul. 2020, Peer-reviewed, Last author

Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver
A.Dan; R. Shimizu; T. Nishikawa; S. Bian; T. Sato
ACM/IEEE Design Automation Conference (DAC), Jul. 2020, Peer-reviewed, Last author, Corresponding author

NASS: Optimizing Secure Inference via Neural Architecture Search
S. Bian; W. Jian, Q. Lu; T. Sato
European Conference on Artificial Intelligence (ECAI), Jun. 2020, Peer-reviewed, Last author

Measurement and Modeling of Ambient-air-induced Degradation in Organic Thin-film Transistor
Michihiro Shintani; Michiaki Saito; Kazunori Kuribara; Yasuhiro Ogasahara; Takashi Sato
IEEE Transactions on Semiconductor Manufacturing (TSM), May 2020, Peer-reviewed, Last author

Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs
Hiroki Tsukamoto; Michihiro Shintani; Takashi Sato
IEEE Transactions on Semiconductor Manufacturing (TSM), May 2020, Peer-reviewed, Last author

Ed-PUF: Event Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System
Y. Zheng; X. Zhao; T. Sato; Y. Cao; C.-H. Chang
IEEE Transactions on Information Forensics and Security (TIFS), Mar. 2020, Peer-reviewed

Recovery-aware Bias-stress Degradation Model for Organic Thin-film Transistors Considering Drain and Gate Bias Voltages
K. Oshima; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
Japanese Journal of Applied Physics (JJAP), Feb. 2020, Peer-reviewed, Last author

A Tuning-free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation
Y. Kume; S. Bian; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2020, Peer-reviewed, Last author

GPU-based Ising Computing for Solving Max-cut Combinatorial Optimization Problems (accepted)
C. Cook; H. Zhao; T. Sato; M. Hiromoto; S. Tan
Integration, the VLSI Journal, Dec. 2019, Peer-reviewed

Parameter Extraction Procedure for Surface-potential-based SiC MOSFET Model
M. Shintani; H. Tsukamoto; T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Oct. 2019, Peer-reviewed, Last author

A Tuning-free Reservoir of MOSFET Crossbar Array for Inexpensive Hardware Realization of Echo State Network
Y. Kume; M. Hiromoto; T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2019, Peer-reviewed, Last author

Improved Multiplier Architecture on ASIC for RLWE-based Key Exchange
T. Ono; S. Bian; T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2019, Peer-reviewed, Last author

Estimation of NBTI-induced Timing Degradation Considering Duty Ratio
K. Oshima; S. Bian; T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2019, Peer-reviewed

Heart Rate Estimation During Exercise from Photoplethysmographic Signals Using Convolutional Neural Network
M. Nakamura; T. Sato
Biomedical Circuits and Systems Conference (BIOCAS), Oct. 2019, Peer-reviewed, Last author, Corresponding author

Experimental Study of Bias Stress Degradation of Organic Thin Film Transistors
K. Oshima; M. Saito; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2019, Peer-reviewed, Last author

A Three-level Active Gate Drive Circuit for Power MOSFETs Utilizing a Generic Gate Driver IC
M. Shintani; K. Oishi; T. Sato
International Conference on Silicon Carbide and Related Materials (ICSCRM), Sep. 2019, Peer-reviewed, Last author

OCM-PUF: An Organic Current Mirror PUF With Enhanced Resilience to Device Degradation
Z. Qin; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS), Jul. 2019, Peer-reviewed, Last author

Filianore: Better Multiplier Architectures for LWE-based Post-quantum Key Exchange
S. Bian; M. Hiromoto; T. Sato
ACM/IEEE Design Automation Conference (DAC), Jun. 2019, Peer-reviewed, Last author

Study on Statistical Parameter Extraction of Power MOSFET Model by Principal Component Analysis
H. Tsukamoto; M. Shintani; T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2019, Peer-reviewed, Last author, Corresponding author

A Compact Model of I-V Characteristic Degradation for Organic Thin Film Transistors
M. Saito; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2019, Peer-reviewed, Last author, Corresponding author

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference
S. Bian; M. Hiromoto; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2019, Peer-reviewed, Last author

Hardware-accelerated Secured Naive Bayesian Filter Based on Partially Homomorphic Encryption
S. Bian; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Feb. 2019, Peer-reviewed, Last author

Feasibility of a Low-power, Low-voltage Complementary Organic Thin Film Transistor Buskeeper Physical Unclonable Function
Y. Ogasahara; K. Kuribara; M. Shintani; T. Sato
Japanese Journal of Applied Physics (JJAP), Jan. 2019, Peer-reviewed, Last author

Towards Practical Homomorphic Email Filtering: A Hardware-accelerated Secure Naive Bayesian Filter
S. Bian; M. Hiromoto; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2019, Peer-reviewed, Last author

Surface-potential-based Silicon Carbide Power MOSFET Model for Circuit Simulation
M. Shintani; Y. Nakamura; K. Oishi; M. Hiromoto; T. Hikihara; T. Sato
IEEE Transactions on Power Electronics (TPEL), Dec. 2018, Peer-reviewed, Last author

A Transient Approach for Input Capacitance Characterization of Power Devices (Invited)
T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2018, Peer-reviewed, Invited, Lead author, Last author, Corresponding author

Measurement and Modeling of Frequency Degradation of an oTFT Ring Oscillator
M. Saito; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2018, Peer-reviewed, Last author

An Experimental Design of Robust Current-mode Arbiter PUF Using Organic Thin Film Transistors
Z. Qin; M. Shintani; K. Kuribara; Y. Ogasahara; T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2018, Peer-reviewed, Last author

Enhancing the Solution Quality of Hardware Ising-model Solver via Parallel Tempering
H. Gyoten; M. Hiromoto; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2018, Peer-reviewed

Initial Parameter Extraction Procedure for Surface-potential-based SiC MOSFET Model
M. Shintani; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2018, Peer-reviewed

On the Reset Operation of Organic Cross-coupled Inverter
M. Saito; M. Shintani; K. Kuribara; Y. Ogasahara; M. Hiromoto; T. Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2018, Peer-reviewed, Last author

MRO-PUF: Physically Unclonable Function With Enhanced Resistance Against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator
M. Hiromoto; M. Yoshinaga; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2018, Peer-reviewed, Last author
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Efficient Mini-batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update
S. Yamamori; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2018, Peer-reviewed
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Modeling of Interelectrode Parasitic Elements of V-groove SiC MOSFET
R. Zhou; M. Shintani; M. Hiromoto; T. Sato
Nonlinear Theory and Its Applications, IEICE, Jul. 2018, Peer-reviewed

Fast and Robust Heart Rate Estimation from Videos Through Dynamic Region Selection
Y. Fujita; M. Hiromoto; T. Sato
International Engineering in Medicine and Biology Conference (EMBC), Jul. 2018, Peer-reviewed, Last author

Interpolation-based Object Detection Using Motion Vectors for Embedded Real-time Tracking Systems
T. Ujiie; M. Hiromoto; T. Sato
IEEE Embedded Vision Workshop, Jun. 2018, Peer-reviewed, Last author

DWE: Decrypting Learning With Errors With Errors
S. Bian; M. Hiromoto; T. Sato
ACM/IEEE Design Automation Conference (DAC), Jun. 2018, Peer-reviewed, Last author

Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks
Y. Tanaka; S. Bian; M. Hiromoto; T. Sato
IEEE Transactions on Circuits and Systems--II: Express Briefs (TCASII), May 2018, Peer-reviewed
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RRAM/CMOS-hybrid Architecture of Annealing Processor for Fully Connected Ising Model
S. Matsumoto; H. Gyoten; M. Hiromoto; T. Sato
IEEE International Memory Workshop (IMW), May 2018, Peer-reviewed

A Plotter-based Automatic Measurements and Statistical Characterization of Multiple Discrete Power Devices
M. Shintani; B. N. Dauphin; K. Oishi; M. Hiromoto; T. Sato
International power electronics conference (IPEC), May 2018, Peer-reviewed, Last author

Coin Flipping PUF: A New PUF With Improved Resistance Against Machine Learning Attacks
Y. Tanaka; S. Bian; M. Hiromoto; T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS), May 2018, Peer-reviewed
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Mechanically and Electrically Robust Metal-mask Design for Organic CMOS Circuits
M. Shintani; Z. Qin; K. Kuribara; Y. Ogasahara; M. Hiromoto; T. Sato
Japanese Journal of Applied Physics (JJAP), Mar. 2018, Peer-reviewed

Electrical and Thermal Characterization of SiC Power MOSFET (Invited)
T. Sato; K. Oishi; M. Hiromoto; M. Shintani
China Semiconductor Technology International Conference (CSTIC), Mar. 2018, Peer-reviewed, Invited

A Study on NBTI-induced Delay Degradation Considering Stress Frequency Dependence
Z. Shin; S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2018, Peer-reviewed

Ising-PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter-PUFs
H. Awano; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2018, Peer-reviewed

Efficient Parameter-extraction of SPICE Compact Model Through Automatic Differentiation
M. Shintani; M. Hiromoto; T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2018, Peer-reviewed

A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
Y. Tanaka; S. Bian; M. Hiromoto; T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2018, Peer-reviewed

A Feasibility Study of Annealing Processor for Fully-connected Ising Model Based on Memristor/CMOS Hybrid Architecture
S. Matsumoto; H. Gyoten; M. Hiromoto; T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2018, Peer-reviewed, Last author

Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Z. Shin; S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2018, Peer-reviewed

Fast and Robust Heart Rate Estimation Using Inexpensive Cameras Through Dynamic Region Selection
Y. Fujita; M. Hiromoto; T. Sato
IEEE Conference on Biomedical and Health Informatics (BHI), Mar. 2018, Peer-reviewed

Area Efficient Annealing Processor for Ising Model Without Random Number Generator
H. Gyoten; M. Hiromoto; T. Sato
IEICE Transactions on Information and Systems, Feb. 2018, Peer-reviewed
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PARHELIA: Particle-filter-based Heart Rate Estimation from Photoplethysmographic Signals During Physical Exercise
Y. Fujita; M. Hiromoto; T. Sato
IEEE Transactions on Bio-Medical Engineering, Jan. 2018, Peer-reviewed
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Efficient Exploration of Worst Case Workload and Timing Degradation Under NBTI
S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2018, Peer-reviewed

Identification and Application of Invariant Critical Paths Under NBTI Degradation
S. Bian; S. Morita; M. Shintani; H. Awano; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2017, Peer-reviewed
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Efficient Aging-aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation
H. Awano; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2017, Peer-reviewed
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Parameter Extraction for MOSFEET Current Model Using Backward Propagation of Errors
M. Shintani; M. Hiromoto; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2017, Peer-reviewed

A Design-analysis Flow Considering Mechanical Stability of Metal Masks for Organic CMOS Circuits
M. Shintani; K. Kuribara; Y. Ogasahara; M. Hiromoto; T. Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2017, Peer-reviewed

RTN in Scaled Transistors for On-chip Random Seed Generation
A. Mohanty; K. Sutaria; H. Awano; T. Sato; Y. Cao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Aug. 2017, Peer-reviewed

Utilization of Path-clustering in Efficient Stress-control Gate Replacement for NBTI Mitigation
S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2017, Peer-reviewed
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LSTA
Song Bian; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato
Proceedings of the 54th Annual Design Automation Conference 2017, 18 Jun. 2017

LSTA: Learning-based Static Timing Analysis for High-dimensional Correlated On-chip Variations
S. Bian; M. Shintani; M. Hiromoto; T. Sato
ACM/IEEE Design Automation Conference (DAC), Jun. 2017, Peer-reviewed, Last author

Scalable Device Array for Statistical Characterization of BTI-related Parameters
H. Awano; S. Morita; T. Sato
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Apr. 2017, Peer-reviewed

Measurement and Modeling of Gate-drain Capacitance of Silicon Carbide Vertical Double-diffused MOSFET
M. Shintani; Y. Nakamura; M. Hiromoto; T. Hikihara; T. Sato
Japanese Journal of Applied Physics (JJAP), Mar. 2017, Peer-reviewed

Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic
S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2017, Peer-reviewed

Input Capacitance Determination of Power MOSFETs from Switching Trajectories
K. Oishi; M. Shintani; M. Hiromoto; T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2017, Peer-reviewed

SCAM: Secured Content Addressable Memory Based on Homomorphic Encryption
S. Bian; M. Hiromoto; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2017, Peer-reviewed

Device Identification from Mixture of Measurable Characteristics
M. Shintani; K. Oishi; R. Zhou; M. Hiromoto; T. Sato
IEEE Applied Power Electronics Conference and Exposition (APEC), Mar. 2017, Peer-reviewed

Efficient Circuit Failure Probability Calculation Along Product Lifetime Considering Device Aging
H. Awano; M. Hiromoto; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2017, Peer-reviewed

Pattern Based Runtime Voltage Emergency Prediction: An Instruction-aware Block Sparse Compressed Sensing Approach
Y. Chen; M. Shintani; T. Sato; Y. Shi; S. Chang
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2017, Peer-reviewed

Hardware Accelerator of Convolutional Neural Network for Image Recognition and Its Performance Evaluation Platform
T. Ujiie; M. Hiromoto; T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI), Nov. 2016, Peer-reviewed

Path Grouping Approach for Efficient Candidate-selection of Replacing NBTI Mitigation Logic
S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI), Nov. 2016, Peer-reviewed

Thermal Circuit Identification of Power MOSFETs Through In-situ Channel Temperature Estimation
K. Oishi; M. Shintani; M. Hiromoto; T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI), Nov. 2016, Peer-reviewed

Unique Device Identification Framework for Power MOSFETs Using Inherent Device Variation
M. Shintani; K. Oishi; R. Zhou; M. Hiromoto; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2016, Peer-reviewed

Representative Path Approach for Time-efficient NBTI Mitigation Logic Replacement
S. Morita; S. Bian; M. Shintani; M. Hiromoto; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2016, Peer-reviewed

Analysis of Transient Behavior of SiC Power MOSFETs Based on Surface Potential Model and Its Application to Boost Converter
T. Okuda; Y. Nakamura; M. Shintani; T. Sato; T. Hikihara
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Nov. 2016, Peer-reviewed

A Circuit Simulation Model for V-groove SiC Power MOSFET
M. Shintani; K. Oishi; R. Zhou; M. Hiromoto; T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Nov. 2016, Peer-reviewed

Identifications of Thermal Equivalent Circuit for Power MOSFETs Through In-situ Channel Temperature Estimation
K. Oishi; M. Shintani; M. Hiromoto; T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Nov. 2016, Peer-reviewed

Runtime NBTI Mitigtion for Processor Lifespan Extension via Selective Node Control
S. Bian; M. Shintani; Z. Wang; M. Hiromoto; A. Chattopadhyay; T. Sato
IEEE Asian Test Symposium (ATS), Nov. 2016, Peer-reviewed

A Charge Based SiC Power MOSFET Model Considering On-state Resistance
R. Zhou; M. Shintani; M. Hiromoto; T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA), Nov. 2016, Peer-reviewed

A Design Example of Class-E Based Gate Driver for High Frequency Operation of SiC Power MOSFET
M. Shintani; S. Yuchong; H. Sekiya; T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA), Nov. 2016, Peer-reviewed

Path Clustering for Test Pattern Reduction of Variation-aware Adaptive Path Delay Testing
M. Shintani; T. Uezono; K. Hatayama; K. Masu; T. Sato
Journal of Electronic Testing: Theory and Applications (JETTA), Oct. 2016, Peer-reviewed

Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor
T. Ujiie; M. Hiromoto; T. Sato
IEEE Embedded Vision Workshop, Sep. 2016, Peer-reviewed

A Simulation Model for SiC Power MOSFET Based on Surface Potential
Y. Nakamura; M. Shintani; K. Oishi; T. Sato; T. Hikihara
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 2016, Peer-reviewed

A Surface-potential-based Reverse-transfer Capacitance Model for Vertical SiC DMOSFET
M. Shintani; Y. Nakamura; M. Hiromoto; T. Sato
International Conference on Solid State Devices and Materials (SSDM), Sep. 2016, Peer-reviewed

Efficient Aging-aware SRAM Failure Probability Calculation via Particle Filter-based Importance Sampling
H. Awano; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2016, Peer-reviewed
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Fast Estimation of NBTI-induced Delay Degradation Based on Signal Probability
S. Bian; M. Shintani; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2016, Peer-reviewed
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Efficient Transistor-level Timing Yield Estimation via Line Sampling
H. Awano; T. Sato
ACM/IEEE Design Automation Conference (DAC), Jun. 2016, Peer-reviewed, Last author

Workload-aware Worst Path Analysis of Processor-scale NBTI Degradation
S. Bian; M. Shintani; S. Morita; H. Awano; M. Hiromoto; T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2016, Peer-reviewed

Physically Unclonable Function Using RTN-induced Delay Fluctuation in Ring Oscillators
M. Yoshinaga; H. Awano; M. Hiromoto; T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, Peer-reviewed

Circuit Aging - Measurement Techniques
Takashi Sato; Hidetoshi Onodera
IEEE International Reliability Physics Symposium, Monday Tutorial, TU2-6, Apr. 2016, Invited, Lead author

Circuit Aging - Measurement Techniques
Takashi Sato; Hidetoshi Onodera
IEEE International Reliability Physics Symposium, Apr. 2016, Invited

Mitigation of NBTI-induced Timing Degradation in Processor
S. Bian; M. Shintani; Z. Wang; M. Hiromoto; A. Chattopadhyay; T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Mar. 2016, Peer-reviewed

Nonlinear Delay-table Approach for Full-chip NBTI Degradation Prediction
S. Bian; M. Shintani; S. Morita; M. Hiromoto; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2016, Peer-reviewed

A High Power Curve Tracer for Characterizing Full Operational Range of SiC Power Transistors
Y. Nakamura; M. Shintani; T. Sato; T. Hikihara
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2016, Peer-reviewed

Fast Monte Carlo for Timing Yield Estimation via Line Sampling
H. Awano; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2015

An Error Correction Scheme Through Time Redundancy for Enhancing Persistent Soft-error Tolerance of CGRAs
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
IEICE Transactions on Electronics, Jul. 2015, Peer-reviewed
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ECRIPSE: An Efficient Method for Calculating RTN-induced Failure Probability of an SRAM Cell
H. Awano; M. Hiromoto; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2015, Peer-reviewed

Accelerating Random-walk-based Power Grid Analysis Through Error Smoothing
T. Okazaki; M. Hiromoto; T. Sato
The 19th workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2015, Peer-reviewed

Sensorless estimation of global device-parameters based on F<inf>max</inf> testing
Michihiro Shintani; Takashi Sato
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 05 Jan. 2015, Peer-reviewed

On-chip characterization of statistical device degradation
Takashi Sato; Hiromitsu Awano
Circuit Design for Reliability, 01 Jan. 2015, Peer-reviewed

Automation of Model Parameter Estimation for Random Telegraph Noise
H. Shimizu; H. Awano; M. Hiromoto; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2014, Peer-reviewed

Sensorless Estimation of Global Device-parameters Through Fmax Testing
M. Shintani; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2014, Peer-reviewed

A Case Study of Chinese Calligraphic Style Classification Using Deep Neural Network
M. Hiromoto; T. Sato
International Workshop on Smart Info-Media Systems in Asia (SISA), Oct. 2014, Peer-reviewed

A Quadrocopter Automatic Control Contest as an Example of Interdisciplinary Design Education
C. Nitschke; Y. Minami; M. Hiromoto; H. Ohshima; T. Sato
14th International Conference on Control, Automation and Systems (ICCAS 2014), Oct. 2014, Peer-reviewed

A Scalable Device Array for Statistical Device-aging Characterization (Invited)
T. Sato; H. Awano; M. Hiromoto
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2014, Peer-reviewed, Invited

BTIarray: A Time-overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability
H. Awano; M. Hiromoto; T. Sato
IEEE Transactions on Device and Materials Reliability, Sep. 2014, Peer-reviewed

Variability in Device Degradations: Statistical Observation of NBTI for 3996 Transistors
H. Awano; M. Hiromoto; T. Sato
Solid-State Device Research Conference (ESSDERC), Sep. 2014, Peer-reviewed

IDDQ Outlier Screening Through Two-phase Approach: Clustering-based Filtering and Estimation-based Current-threshold Determination
M. Shintani; T. Sato
IEICE Transactions on Information and Systems, Aug. 2014, Peer-reviewed
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Multilevel reliability simulation for IC design
Ketul B. Sutaria; Jyothi B. Velamala; Venkatesa Ravi; Gilson Wirth; Takashi Sato; Yu Cao
Bias Temperature Instability for Devices and Circuits, 01 Jul. 2014, Peer-reviewed

Charge trapping in MOSFETS: BTI and RTN modeling for circuits
Gilson Wirth; Yu Cao; Jyothi B. Velamala; Ketul B. Sutaria; Takashi Sato
Bias Temperature Instability for Devices and Circuits, 01 Jul. 2014, Peer-reviewed

A Variability-aware Adaptive Test Flow for Test Quality Improvement
M. Shintani; T. Uezono; T. Takahashi; K. Hatayama; T. Aikyo; K. Masu; T. Sato
IEEE Transactions on Computer-Aided Design, Jul. 2014, Peer-reviewed

Aging Statistics Based on Trapping/detrapping: Compact Modeling and Silicon Validation
K. B. Sutaria; J. B. Velamala; C. Kim; T. Sato; Y. Cao
IEEE Transactions on Device and Materials Reliability, Jun. 2014, Peer-reviewed

A Low Cost Capacitor Approach for Suppressing Resonance in Power Distribution Networks
K. Yamanaga; H. Yamamoto; T. Sato
International Symposium on Electromagnetic Compatibility, Tokyo (EMC Tokyo), May 2014, Peer-reviewed

Hypersphere Sampling for Accelerating High-dimension and Low-failure Probability Circuit-yield Analysis
S. Hagiwara; T. Date; K. Masu; T. Sato
IEICE Transactions on Electronics, Apr. 2014, Peer-reviewed
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Experimental Validation of Minimum Operating Voltage Estimation for Low Supply Voltage Circuits
T. Sato; J. Kawashima; H. Tsutsui; H. Ochi
International Symposium on Quality Electronic Design (ISQED), Mar. 2014, Peer-reviewed

Automation of Model Parameter Estimation for Random Telegraph Noise
SHIMIZU Hirofumi; AWANO Hiromitsu; HIROMOTO Masayuki; SATO Takashi
IEICE Trans. Fundamentals, 2014

State-dependence of On-chip Power Distribution Network Capacitance
K. Yamanaga; R. Takahashi; S. Hagiwara; K. Masu; T. Sato
IEICE Transactions on Electronics, Jan. 2014, Peer-reviewed
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経時劣化概説
佐藤高史; 橋本昌宜
日本信頼性学会誌, Dec. 2013, Peer-reviewed, Invited

Time Dependent Degradation (Invited)
T. Sato; M. Hashimoto
The Journal of Reliability Engineering Association of Japan, Dec. 2013, Peer-reviewed, Invited

Compact Modeling of Statistical BTI Under Trapping/detrapping
J. B. Velamala; K. B. Sutaria; H. Shimizu; H. Awano; T. Sato; G. Wirth; Y. Cao
IEEE Transactions on Electron Devices, Nov. 2013, Peer-reviewed

Statistical Observation of NBTI and PBTI Degradations
H. Awano; M. Hiromoto; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2013

A Device Array for Flexible BTI Characterization (Invited Talk)
T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2013

Place-and-route Algorithms for a Reliability-oriented Coarse-grained Reconfigurable Architecture Using Time Redundancy
T. Imagawa; M. Hiromoto; H. Tsutsui; H. Ochi; T. Sato
The 18th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2013, Peer-reviewed

Statistical Simulation Methods for Analyzing Performance of Low Supply Voltage Circuits (Invited)
T. Sato
The IEEE 10th International Conference on ASIC (ASICON), Sep. 2013, Peer-reviewed, Invited

Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
S. Zhang; H. Tsutsui; H. Ochi; T. Sato
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jun. 2013, Peer-reviewed

Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
S. Matsuda; T. Imagawa; H. Tsutsui; T. Sato; Y. Nakamura; H. Ochi
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jun. 2013, Peer-reviewed

Fast and Memory-efficient GPU Implementations of Krylov Subspace Methods for Efficient Power Grid Analysis
T. Morishita; H. Tsutsui; H. Ochi; T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, Peer-reviewed

A Cost-effective Selective TMR for Coarse-grained Reconfigurable Architectures Based on DFG-level Vulnerability Analysis
T. Imagawa; H. Tsutsui; H. Ochi; T. Sato
IEICE Transactions on Electronics, Apr. 2013, Peer-reviewed
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Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
IEICE Transactions on Electronics, Apr. 2013, Peer-reviewed
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Logarithmic Modeling of BTI Under Dynamic Circuit Operations: Static, Dynamic and Long-term Prediction
J. B. Velamala; K. B. Sutaria; H. Shimizu; H. Awano; T. Sato; G. Wirth; Y. Cao
IEEE International Reliability Physics Symposium (IRPS), Apr. 2013, Peer-reviewed

Multi-trap RTN Parameter Extraction Based on Bayesian Inference
H. Awano; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2013, Peer-reviewed

High-speed DFG-level SEU Vulnerability Analysis for Applying Selective TMR to Resource-constrained CGRA
T. Imagawa; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2013, Peer-reviewed

Hot-swapping Architecture With Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array
Z. E. Rakossy; M. Hiromoto; H. Tsutsui; T. Sato; Y. Nakamura; H. Ochi
Design, Automation and Test in Europe (DATE), Mar. 2013, Peer-reviewed

A Cost-effective Selective TMR for Heterogeneous Coarse-grained Reconfigurable Architectures Based on DFG-level Vulnerability Analysis
T. Imagawa; H. Tsutsui; H. Ochi; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2013, Peer-reviewed

Device-parameter Estimation Through IDDQ Signatures
M. Shintani; T. Sato
IEICE Transactions on Information and Systems, Feb. 2013, Peer-reviewed
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Realization of Frequency-domain Circuit Analysis Through Random Walk
T. Miyakawa; H. Tsutsui; H. Ochi; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013, Peer-reviewed

An Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013, Peer-reviewed

A Variability-aware Energy-minimization Strategy for Subthreshold Circuits
J. Kawashima; H. Tsutsui; H. Ochi; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2012, Peer-reviewed
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Power Distribution Network Optimization for Timing Improvement With Statistical Noise Model and Timing Analysis
T. Enami; T. Sato; M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2012, Peer-reviewed
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Bayesian Estimation of Multi-trap RTN Parameters Using Markov Chain Monte Carlo Method
H. Awano; H. Tsutsui; H. Ochi; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2012, Peer-reviewed
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Adaptive Current-threshold Determination for Accurate IDDQ Testing
M. Shintani; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2012

The Odd Couple: Antiresonance Control by Two Capacitors of Unequal Series Resistances
K. Yamanaga; T. Sato
The 21st conference on electrical performance of electronic packaging and systems (EPEPS), Oct. 2012, Peer-reviewed

Statistical Aging Under Dynamic Voltage Scaling: A Logarithmic Model Approach
J. B. Velamala; K. B. Sutaria; H. Shimizu; H. Awano; T. Sato; Y. Cao
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2012, Peer-reviewed

Physics Matters: Statistical Aging Prediction Under Trapping/detrapping
J. B. Velamala; K. B. Sutaria; T. Sato; Y. Cao
ACM/IEEE Design Automation Conference (DAC), Jun. 2012, Peer-reviewed

Aging Statistics Based on Trapping/detrapping: Silicon Evidence, Modeling and Long-term Prediction
J. B. Velamala; K. B. Sutaria; T. Sato; Y. Cao
IEEE International Reliability Physics Symposium (IRPS), Apr. 2012, Peer-reviewed

A Bayesian-based Process Parameter Estimation Using IDDQ Current Signature
M. Shintani; T. Sato
IEEE VLSI Test Symposium (VTS), Apr. 2012, Peer-reviewed

Hardware Architecture for Accelerating Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2012, Peer-reviewed

GPU Acceleration of Cycle-based Soft-error Simulation for Reconfigurable Array Architectures
T. Imagawa; T. Oue; H. Tsutsui; H. Ochi; T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2012, Peer-reviewed

Statistical Observations of NBTI-induced Threshold Voltage Shifts on Small Channel-area Devices
T. Sato; H. Awano; H. Shimizu; H. Tsutsui; H. Ochi
International Symposium on Quality Electronic Design (ISQED), Mar. 2012, Peer-reviewed

Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Jan. 2012, Peer-reviewed

Getting the Most Out of IDDQ Testing
M. Shintani; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2011

Statistical Aging Prediction and Characterization Using Trapping/detrapping Based NBTI Models
J. B. Velamala; T. Sato; Y. Cao
Workshop on variability modeling and characterization (VMC), Nov. 2011

A Device Array for Efficient Bias-temperature Instability Measurements
T. Sato; T. Kozaki; T. Uezono; H. Tsutsui; H. Ochi
Solid-State Device Research Conference (ESSDERC), Sep. 2011, Peer-reviewed

A Design Strategy for Sub-threshold Circuits Considering Energy-minimization and Yield-maximization
J. Kawashima; H. Tsutsui; H. Ochi; T. Sato
IEEE International SOC Conference (SOCC), Sep. 2011, Peer-reviewed

A Stress-parallelized Device Array for Efficient Bias-temperature Stability Measurement
T. Sato; T. Kozaki; T. Uezono; H. Tsutsui; H. Ochi
The 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y), Jun. 2011, Peer-reviewed

Acceleration of Random-walk-based Linear Circuit Analysis Using Importance Sampling
T. Miyakawa; K. Yamanaga; H. Tsutsui; H. Ochi; T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2011, Peer-reviewed

A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2011, Peer-reviewed

Linear Time Calculation of On-chip Power Distribution Network Capacitance Considering State-dependence
S. Hagiwara; K. Yamanaga; R. Takahashi; K. Masu; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2010, Peer-reviewed
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Reliability Evaluation Environment for Exploring Design Space of Coarse-grained Reconfigurable Architectures
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2010, Peer-reviewed
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Sequential Importance Sampling for Low-probability and High-dimensional SRAM Yield Analysis
K. Katayama; S. Hagiwara; H. Tsutsui; H. Ochi; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010, Peer-reviewed, Last author, Corresponding author

A Transistor-array for Parallel BTI-effects Measurements
T. Uezono; T. Kozaki; H. Ochi; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2010

A Tool Chain for Generating SEU-vulnerability Map for Coarse-grained Reconfigurable Architecture
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
The 25th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jul. 2010, Peer-reviewed

A Routing Architecture Exploration for Coarse-grained Reconfigurable Architecture With Automated SEU-tolerance Evaluation
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
IEEE International SOC Conference (SOCC), Jul. 2010, Peer-reviewed

Application of Generalized Scattering Matrix for Prediction of Power Supply Noise
K. Yamanaga; K. Masu; T. Sato
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Jun. 2010, Peer-reviewed

Decomposition of Drain-current Variation Into Gain-factor and Threshold Voltage Variations
T. Sato; T. Uezono; N. Nakayama; K. Masu
IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Peer-reviewed

Small Delay and Area Overhead Process Parameter Estimation Through Path-delay Inequalities
T. Uezono; T. Takahashi; M. Shintani; K. Hatayama; K. Masu; H. Ochi; T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Peer-reviewed

A Universal Equivalent Circuit Model for Ceramic Capacitors
K. Yamanaga; S. Amakawa; K. Masu; T. Sato
IEICE Transactions on Electronics, Apr. 2010, Peer-reviewed

Path Clustering for Adaptive Test
T. Uezono; T. Takahashi; M. Shintani; K. Hatayama; K. Masu; H. Ochi; T. Sato
IEEE VLSI Test Symposium (VTS), Apr. 2010, Peer-reviewed

A Time-slicing Ring Oscillator for Capturing Time-dependent Delay Degradation and Power Supply Voltage Fluctuation
T. Uezono; K. Masu; T. Sato
IEICE Transactions on Electronics, Mar. 2010, Peer-reviewed

Impact of Self-heating in Wire Interconnection on Timing
T. Kanamoto; T. Okumura; K. Furukawa; H. Takafuji; A. Kurokawa; K. Hachiya; T. Sakata; M. Tanaka; H. Nakashima; H. Masuda; T. Sato; M. Hashimoto
IEICE Transactions on Electronics, Mar. 2010, Peer-reviewed

Robust Importance Sampling for Efficient SRAM Yield Analysis
T. Date; S. Hagiwara; K. Masu; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2010, Peer-reviewed

Linear Time Calculation of State-dependent Power Distribution Network Capacitance
S. Hagiwara; K. Yamanaga; R. Takahashi; K. Masu; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2010, Peer-reviewed

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis
Z. Huang; A. Kurokawa; M. Hashimoto; T. Sato; M. Jiang; Y. Inoue
IEEE Transactions on Computer-Aided Design, Feb. 2010, Peer-reviewed

An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability
T. Sakata; T. Okumura; A. Kurokawa; H. Nakashima; H. Masuda; T. Sato; M. Hashimoto; K. Hachiya; K. Furukawa; M. Tanaka; H. Takafuji; T. Kanamoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2009, Peer-reviewed

Accurate Array-based Measurement for Subthreshold-current of MOS Transistors
T. Sato; H. Ueyama; N. Nakayama; K. Masu
IEEE Journal of Solid-State Circuits, Nov. 2009, Peer-reviewed

On-die Parameter Extraction from Path-delay Measurements
T. Takahashi; T. Uezono; M. Shintani; K. Masu; T. Sato
IEEE Asian solid-state circuit conference (ASSCC), Nov. 2009, Peer-reviewed

Interconnect Modeling: A Physical Design Perspective (Invited)
A. Kurokawa; T. Sato; T. Kanamoto; M. Hashimoto
IEEE Transactions on Electron Devices, Sep. 2009, Peer-reviewed, Invited

An Adaptive Test for Parametric Faults Based on Statistical Timing Information
M. Shintani; T. Uezono; T. Takahashi; H. Ueyama; T. Sato; K. Hatayama; T. Aikyo; K. Masu
IEEE Asian Test Symposium (ATS), Sep. 2009, Peer-reviewed

Bridging the Gap Between Laboratory Measurement and Simulation Model (Invited)
T. Sato
International Workshop on Emerging Circuits and Systems (IWECS), Jul. 2009, Invited

Two-dimensional Moment Method for Analyzing Current Distribution of a Ceramic Capacitor
K. Yamanaga; S. Amakawa; T. Sato; K. Masu
International Symposium on Electromagnetic Compatibility (EMC Kyoto), Jul. 2009, Peer-reviewed

Physical Design Challenges to Nano-CMOS Circuits (Invited)
K. Masu; N. Ishihara; N. Nakayama; T. Sato; S. Amakawa
IEICE Electronics Express (ELEX), Jun. 2009, Peer-reviewed, Invited

Application of the EMI Decoupling Circuit Consisting of Two Capacitors and a Power Trace to Quad Flat Package (QFP) LSI
SASAKI Hideki; HARADA Takashi; KURIYAMA Toshihide; SATO Takashi; MASU Kazuya
The IEICE transactions on communications B, May 2009, Peer-reviewed

Application of the EMI Decoupling Circuit Consisting of Two Capacitors and a Power Trace to Quad Flat Package (QFP) LSI
H. Sasaki; T. Harada; T. Kuriyama; T. Sato; K. Masu
IEICE Transactions on Communications (Japanese Edition), May 2009, Peer-reviewed

Reduction approach of leak current variation due to process variation
佐方剛; 黒川敦; 奥村隆昌; 中島英斉; 増田弘生; 佐藤高史; 橋本昌宜; 蜂屋孝太郎; 古川且洋; 田中正和; 高藤浩資; 金本俊幾
IEICE (Karuizawa) Workshop on Circuits and Systems, Apr. 2009, Peer-reviewed

2-port Modeling Technique for Surface-mount Passive Components
K. Yamanaga; T. Sato; K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2009, Peer-reviewed

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
T. Okumura; A. Kurokawa; H. Masuda; T. Kanamoto; M. Hashimoto; H. Takafuji; H. Nakashima; N. Ono; T. Sakata; T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2009, Peer-reviewed

One-shot Voltage-measurement Circuit Utilizing Process Variation
T. Uezono; T. Sato; K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2009, Peer-reviewed

Analytical Estimation of Path-delay Variation for Multi-threshold CMOS Circuits
S. Hagiwara; T. Sato; K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2009, Peer-reviewed

S-parameter-based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-embedding
S. Amakawa; K. Yamanaga; H. Ito; T. Sato; N. Ishihara; K. Masu
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2009, Peer-reviewed

A MOS Transistor Array With Pico-ampere Order Precision for Accurate Characterization of Leakage Current Variation
T. Sato; H. Ueyama; N. Nakayama; K. Masu
IEEE Asian solid-state circuit conference (ASSCC), Nov. 2008, Peer-reviewed

Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis
T. Enami; M. Hashimoto; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2008, Peer-reviewed

An Efficient Extraction of Random and Systematic Gate-length Variation Through Poly-Si Resistor Measurement
N. Nakayama; T. Sato; H. Ueyama; K. Masu
Workshop on Test Structure Design for Variability Characterization, Nov. 2008, Peer-reviewed

Non-invasive Direct Probing for On-chip Voltage Measurement
T. Sato; K. Yamanaga; K. Masu
International SoC Design Conference (ISOCC), Nov. 2008, Peer-reviewed

Accurate Parasitic Inductance Determination of a Ceramic Capacitor Through 2-port Measurements
K. Yamanaga; T. Sato; K. Masu
The 17th topical meeting on electrical performance of electronic packaging (EPEP), Oct. 2008, Peer-reviewed

Layout-aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
K. Yamada; T. Sato; N. Nakayama; S. Amakawa; K. Masu; S. Kumashiro
IEICE Transactions on Electronics, Jul. 2008, Peer-reviewed

Non-parametric Statistical Static Timing Analysis: An SSTA Framework for Arbitrary Distribution
M. Imai; T. Sato; N. Nakayama; K. Masu
ACM/IEEE Design Automation Conference (DAC), Jun. 2008, Peer-reviewed

On-chip Differential and Common Mode Voltage Measurement Using Off-chip Referenced Twin Probing
K. Yamanaga; T. Sato; K. Masu
IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2008, Peer-reviewed

Substrate-geometry Aware 2-port Modeling for Surface-mount Passive Components
K. Yamanaga; T. Sato; K. Masu
19th International Zurich Symposium on Electromagnetic Compatibility, May 2008, Peer-reviewed

Analysis of output transition time variation due to Vth variations
奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任
IEICE (Workshop) on Circuits and Systems, Apr. 2008, Peer-reviewed

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
M. Imai; T. Sato; N. Nakayama; K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2008, Peer-reviewed

Application of Correlation-based Regression Analysis for Improvement of Power Distribution Network
S. Hagiwara; T. Uezono; T. Sato; K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2008, Peer-reviewed

Timing Analysis Considering Temporal Supply Voltage Fluctuation
M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera
IEICE Transactions on Information and Systems, Mar. 2008, Peer-reviewed

Determination of Optimal Polynomial Regression Function to Decompose On-die Systematic and Random Variations
T. Sato; H. Ueyama; N. Nakayama; K. Masu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2008, Peer-reviewed

Validation of a Full-chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-chip Delay Measurement
Y. Ogasahara; T. Enami; M. Hashimoto; T. Sato; T. Onoye
IEEE Transactions on Circuits and Systems--II: Express Briefs (TCASII), Oct. 2007, Peer-reviewed

A Study on Variation-component Decomposition Using Polynomial Smoothing Function
T. Sato; H. Ueyama; N. Nakayama; K. Masu
The 14th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2007, Peer-reviewed

Weakness Identification for Effective Repair of Power Distribution Network
T. Sato; S. Hagiwara; T. Uezono; K. Masu
17th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 2007, Peer-reviewed

Proposal of Metrics for SSTA Accuracy Evaluation
H. Kobayashi; N. Ono; T. Sato; J. Iwai; H. Nakashima; T. Okumura; M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2007, Peer-reviewed

A wire-length distribution that models moderate-angled sectioning and underoccupancy of core area
Amakawa Shuhei; Uezono Takumi; Sato Takashi; Masu Kazuya
Proceedings of the IEICE General Conference, 07 Mar. 2007

Improvement of Power Distribution Network Using Correlation-based Regression Analysis
S. Hagiwara; T. Uezono; T. Sato; K. Masu
ACM Great Lakes Symposium on VLSI (GLSVLSI), Mar. 2007, Peer-reviewed

Adaptable Wire-length Distribution With Tunable Occupation Probability
S. Amakawa; T. Uezono; T. Sato; K. Masu
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Mar. 2007, Peer-reviewed

A MOS Transistor-array for Accurate Measurement of Subthreshold Leakage Variation
T. Sato; T. Uezono; S. Hagiwara; K. Okada; S. Amakawa; N. Nakayama; K. Masu
International Symposium on Quality Electronic Design (ISQED), Mar. 2007, Peer-reviewed

A Multi-drop Transmission-line Interconnect in Si LSI
J. Seita; H. Ito; K. Okada; T. Sato; K. Masu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2007, Peer-reviewed

On-chip Thermal Gradient Analysis Considering Interdependence Between Leakage Power and Temperature
T. Sato; J. Ichimiya; N. Ono; M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2006, Peer-reviewed

A Left Handed Material on Si CMOS Chip With Wafer Level Package Process
J. Kim; T. Yammouchi; K. Okada; T. Sato; K. Masu
Asia Pacific Microwave Conference (APMC), Dec. 2006, Peer-reviewed

Thermal Driven Module Placement Using Sequence-pair
M. Okada; C. Kodama; T. Sato; K. Fujiyoshi
Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006, Peer-reviewed

Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation
Y. Ogasahara; T. Enami; M. Hashimoto; T. Sato; T. Onoye
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006, Peer-reviewed

A Method to Derive SSO Design Rule Considering Jitter Constraint
K. Hachiya; H. Kobayashi; T. Okumura; T. Sato; H. Oka
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2006, Peer-reviewed

A time-slicing ring oscillator for capturing instantaneous delay degradation and power supply voltage drop
Takashi Sato; Yu Matsumoto; Koji Hirakimoto; Michio Komoda; Junichi Mano
Proceedings of the Custom Integrated Circuits Conference, 2006, Peer-reviewed

Successive pad assignment for minimizing supply voltage drop
T. Sato; M. Hashimoto; H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion
T. Sato; M. Hashimoto; H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
T. Sato; J. Ichimiya; N. Ono; K. Hachiya; M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

Design and Measurement of an Inductance-oscillator for Analyzing On-chip Inductance Impact on Wire Delay
T. Sato; H. Masuda
Journal of Analog Integrated Circuits and Signal Processing, Mar. 2005, Peer-reviewed

Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion
T. Sato; M. Hashimoto; H. Onodera
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
T. Sato; J. Ichimiya; N. Ono; K. Hachiya; M. Hashimoto
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

Timing Analysis Considering Temporal Supply Voltage Fluctuation
M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads
T. Sato; M. Hashimoto; H. Onodera
The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2004, Peer-reviewed

Probabilistic Crosstalk Delay Estimation for ASICs
K. Takeuchi; K. Yanagisawa; T. Sato; K. Sakamoto; S. Hojo
IEEE Transactions on Computer-Aided Design, Sep. 2004, Peer-reviewed

Approximation Formula Approach for the Efficient Extraction of On-chip Inductance
A. Kurokawa; T. Sato; H. Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2003, Peer-reviewed

Spice Up Your MOSFET Modeling
Y. Cao; M. Orshansky; T. Sato; D. Sylvester; C. Hu
IEEE Circuits and Devices Magazine, Jul. 2003, Peer-reviewed

Bi-directional Closed-form Transformation Between On-chip Coupling Noise Waveforms and Interconnect Delay Change Curves
T. Sato; Y. Cao; K. Agarwal; D. Sylvester; C. Hu
IEEE Transactions on Computer-Aided Design, May 2003, Peer-reviewed

遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法
金本俊幾; 佐藤高史; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 小林宏之; 橋本昌宜
情報処理学会論文誌, May 2003, Peer-reviewed

A Statistical Methodology for Screening Inductance Dominated Interconnects in Timing Analysis
T. Kanamoto; T. Sato; A. Kurokawa; Y. Kawakami; H. Oka; T. Kitaura; H. Kobayashi; M. Hashimoto
Information Processing Society of Japan, May 2003, Peer-reviewed

Fast On-chip Inductance Extraction of VLSI Including Angled Interconnects
A. Kurokawa; K. Hachiya; T. Sato; K. Tokumasu; H. Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2003, Peer-reviewed

Design and Measurement of an Inductance-oscillator for Analyzing Inductance Impact on On-chip Interconnect Delay
T. Sato; H. Masuda
International Symposium on Quality Electronic Design (ISQED), Mar. 2003, Peer-reviewed

Approximate Formulae Approach for Efficient Inductance Extraction
A. Kurokawa; T. Sato; H. Masuda
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2003, Peer-reviewed

Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay Using Electrical and Physical Parameter-based RSF
T. Sato; T. Kanamoto; A. Kurokawa; Y. Kawakami; H. Oka; T. Kitaura; H. Kobayashi; M. Hashimoto
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2003, Peer-reviewed

Efficient Generation of Delay Change Curves for Noise-aware Static Timing Analysis
K. Agarwal; Y. Cao; T. Sato; D. Sylvester; C. Hu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2002, Peer-reviewed

Accurate In-situ Measurement of Noise Peak and Delay Induced by Interconnect Coupling
T. Sato; D. Sylvester; Y. Cao; C. Hu
IEEE Journal of Solid-State Circuits, Oct. 2001, Peer-reviewed

New Approaches to Noise-aware Static Timing Analysis
Y. Cao; T. Sato; X. Huang; C. Hu; D. Sylvester
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Dec. 2000, Peer-reviewed

Characterization of Interconnect Coupling Noise Using In-situ Delay-change Curve Measurements
T. Sato; Y. Cao; D. Sylvester; C. Hu
13th IEEE International ASIC/SOC Conference, Sep. 2000, Peer-reviewed

New Paradigm of Predictive CMOS Modeling for Early Circuit Simulation
Y. Cao; T. Sato; M. Orshansky; D. Sylvester; C. Hu
IEEE Custom Integrated Circuits Conference (CICC), May 2000, Peer-reviewed

A 5 GBytes/s Data Transfer Scheme With Bit-to-bit Skew Control for Synchronous DRAM
T. Sato; Y. Nishio; T. Sugano; Y. Nakagome
IEEE Journal of Solid-State Circuits, May 1999, Peer-reviewed

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GGPinReal: Verifiable Privacy-preserving logic circuit evaluation platform via LWE based Garbled Circuit over TFHE
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情報処理学会SLDM研究発表会, Nov. 2024

高誘電率ポリマー誘電体の大気コーティングによる有機薄膜トランジスタの低電圧動作
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通信需要と電波環境の同時変化環境における基地局 ON/OFF 最適化
中平俊朗; 山本高至; 佐藤高史
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誤り耐性量子コンピュータの実現に向けた表面符号デコーダの極低温CMOS集積回路による実装検討
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DAシンポジウム, Aug. 2024

4.2Kでの65nmバルクpMOSトランジスタにおけるランダムテレグラフノイズの評価
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DAシンポジウム, Aug. 2024

ニューロモーフィックチップAkidaにおける高電力効率な推論のためのゼロアウェアなSNN学習法
羽原丈博; 佐藤高史; 粟野皓光
DAシンポジウム, Aug. 2024

180nmプロセス試作チップに基づくトランジスタのばらつきを利用したハードウェアESNの検討
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DAシンポジウム, Aug. 2024

Optimizing Prime Factorization Scalability via Quantum Annealing with Analytical and Pattern-Based Variable Reduction under Partial Constraints
Xinyi Guo; Geguang Miao; Shinichi Nishizawa; Shinji Kimura; Takashi Sato
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信学技報 SRW SeMI CNR, Jan. 2023

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信学技報 MICT研究会, Jan. 2023, Last author

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松岡航太郎; 星月祐介; 佐藤高史; Song Bian
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粟野皓光; 清水裕史; 筒井弘; 越智裕之; 佐藤高史
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A-3-14 Measurement of Subthreshold Leakage Current Using a MOS Transistor-Array
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A-3-7 Quantitative evaluation of power supply network using voltage drop correlation
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Power MOSFETs Identification Using Machine Learning on Characteristic Curves (電子通信エネルギー技術)
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H-2-20 Performance Evaluation of Conductive Object Localization Using Electric Field Gestural Sensor with Mesh Electrode
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Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillators
YOSHINAGA Motoki; AWANO Hiromitsu; HIROMOTO Masayuki; SATO Takashi
Technical report of IEICE. VLD, 02 Mar. 2015

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C-12-18 An automated estimation of MOS transistors' interface-state numbers using EM algorithm
Shimizu Hirofumi; Tsutsui Hiroshi; Ochi Hiroyuki; Sato Takashi
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Shintani Michihiro; Takahashi Tomoyuki; Ueyama Hiroyuki; Uezono Takumi; Sato Takashi; Hatayama Kasumi; Aikyo Takashi; Masu Kazuya
Proceedings of the IEICE General Conference, 04 Mar. 2009

D-10-17 Critical-Path Clustering for Adaptive Test
Uezono Takumi; Takahashi Tomoyuki; Ueyama Hiroyuki; Shintani Michihiro; Sato Takashi; Masu Kazuya
Proceedings of the IEICE General Conference, 04 Mar. 2009

A-3-2 A Sensitivity Study of Standard Cell Delay to Voltage Fluctuation and Process Variations
Takahashi Tomoyuki; Ueyama Hiroyuki; Hagiwara Shiho; Sato Takashi; Masu Kazuya
Proceedings of the Society Conference of IEICE, 02 Sep. 2008

A Method to Derive SSO Design Rule Considering Jitter Constraint
HACHIYA Koutaro; KOBAYASHI Hiroyuki; OKUMURA Takaaki; SATO Takashi; OKA Hiroki
IEICE transactions on fundamentals of electronics, communications and computer sciences, 01 Apr. 2006

完全準同型暗号におけるBNNを用いた高速な秘匿推論手法の実装と評価
橋詰陽太; 古川修平; 松本直樹; 伴野良太郎; 松岡航太郎; 佐藤高史
情報処理学会第84回全国大会, Mar. 2022, Last author

高精度過渡解析に向けたスイッチング波形によるパワーMOSFETゲート入力容量測定手法
西谷洋太; 新谷道広; 井上美智子; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Mar. 2022, Last author

Non-normal Model Parameter Generation\\for Variation-Aware Circuit Simulation
Takashi Sato; Hiroki Tsukamoto; Song Bian; Michihiro Shintani
IEICE Tech. Rep., Nov. 2021, Invited, Lead author, Corresponding author

量子計算の誤り軽減のための量子ビット初期配置手法
瀬川七央; 佐藤高史
第34回回路とシステムワークショップ論文集, Aug. 2021, Peer-reviewed, Last author

商用Wi-Fiデバイスを使用したピーク位置推定に基づく心拍変動の推定
白神樹; 佐藤高史
第34回回路とシステムワークショップ論文集, Aug. 2021, Peer-reviewed, Last author

複数カメラと粒子フィルタを用いた体動にロバストな心拍推定手法
一柳優太; 佐藤高史
第34回回路とシステムワークショップ論文集, Aug. 2021, Peer-reviewed, Last author

n型有機薄膜トランジスタにおけるバイアス・ストレス特性変動物理メカニズムの実験的評価
大島國弘; 栗原一徳; 辺松; 佐藤高史
DAシンポジウム, Aug. 2020, Peer-reviewed, Last author

畳み込みニューラルネットワークを利用した光電容積脈波からの運動時心拍推定手法
中村公暉; 廣本正之; 佐藤高史
回路とシステムワークショップ, Aug. 2019, Peer-reviewed, Last author

有機薄膜トランジスタの実測に基づくバイアス・ストレス劣化の要因とモデル化に関する検討
大島國弘; 齋藤成晃; 新谷道広; 栗原一徳; 小笠原泰弘; 佐藤高史
DA シンポジウム, Aug. 2019, Peer-reviewed, Last author

レプリカ交換イジングモデルソルバにおけるレプリカトポロジーと温度割当方法に関する検討
党璋; 佐藤高史
信学技報 VLD研究会, May 2019, Last author

Towards Practical Homomorphic Email Filtering: A Hardware-accelerated Secure Naive Bayesian Filter
S. Bian; M. Hiromoto; T. Sato
IEICE Technical Report, Feb. 2019, Last author

レプリカセンサを用いたNBTIによる回路特性変動予測に関する検討
大島國弘; 辺松; 廣本正之; 佐藤高史
信学技報 VLD研究会(デザインガイア), Nov. 2018, Last author

NBTI劣化によるArbiter PUFの応答変化に関する検討
小野龍輝; 田中悠貴; 新瑞徳; 辺松; 廣本正之; 佐藤高史
電子情報通信学会総合大会, Sep. 2018, Last author

メモリスタを用いた等価な応答を返すPUF対の検討
田中悠貴; 辺松; 廣本正之; 佐藤高史
DA シンポジウム, Aug. 2018, Peer-reviewed, Last author

Approximate computing を用いたLWE暗号の高効率復号回路
辺松; 廣本正之; 佐藤高史
DA シンポジウム, Aug. 2018, Peer-reviewed

ストカスティック計算を用いたニューラルネットワークハードウェアのための省面積積和演算器
名倉健太; 廣本正之; 佐藤高史
信学技報 VLSI設計技術研究会, Jun. 2018

多ビットの相互作用をもつ全接続イジングモデルのためのRRAMアニーリングプロセッサ
松本章吾; 業天英範; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2018, Peer-reviewed

有機トランジスタによるBuskeeper PUFの試作と連続測定のためのリセット回路の検討
齊藤成晃; 新谷道広; 栗原一徳; 小笠原泰弘; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2018, Peer-reviewed

畳み込みニューラルネットワークの周波数領域学習による演算量削減
三宅哲史; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2018, Peer-reviewed

動画像コーデックの動きベクトル援用によるCNN物体検出の負荷緩和
氏家隆之; 廣本正之; 佐藤高史
情報処理学会第210回コンピュータビジョンとイメージメディア研究発表会, Jan. 2018

双安定リング回路の収束時間により瞬時値応答を得る発振回路PUF
田中悠貴; 辺松; 廣本正之; 佐藤高史
信学技報 VLD研究会(デザインガイア), Nov. 2017

SiCパワーMOSFETの特性測定とモデル化(招待)
佐藤高史; 大石一輝; 廣本正之; 新谷道広
信学技報 SDM研究会, Nov. 2017, Invited

汎用ゲートドライバICを利用したパワーMOSFETの3レベルアクティブゲート駆動回路
大石一輝; 新谷道広; 廣本正之; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Nov. 2017

有機トランジスタCMOS回路製造のためのメタルマスクの要素設計ルールに関する一検討
Qin Zhaoxing; 新谷道広; 廣本正之; 栗原一徳; 小笠原泰弘; 佐藤高史
電子情報通信学会総合大会, Sep. 2017

Secured Content Addressable Memory Based on Homomorphic Encryption
S. Bian; M. Hiromoto; T. Sato
DA Symposium, Aug. 2017, Peer-reviewed

チャレンジヒステリシス特性を有するPUFの設計とシミュレーションに基づく性能評価
粟野皓光; 佐藤高史
DA シンポジウム, Aug. 2017, Peer-reviewed

特性曲線を特徴ベクトルとした機械学習によるパワーデバイスの個体識別
ベンジャミンドーファン; 大石一輝; 新谷道広; 廣本正之; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Jul. 2017

プロッタを利用したディスクリートパワーデバイスの自動測定装置
ベンジャミンドーファン; 大石一輝; 新谷道広; 廣本正之; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Jun. 2017

Electro-Thermal Simulation for Power Converters Using Circuit Simulators : Power MOSFET Modeling Considering Self-Heating
佐藤高史; 大石一輝; 新谷道広; 廣本正之
回路とシステムワークショップ, May 2017, Peer-reviewed, Invited

特性測定に基づくパワーデバイスの自己発熱モデルを利用した電力変換回路の電気・熱連成解析
大石一輝; 新谷道広; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2017, Peer-reviewed

Time-dependent Model for Threshold Voltage Shift Considering Permanent/Recoverable Components of Transistor Degradation
新瑞徳; 森田俊平; 新谷道新; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2017, Peer-reviewed

Line samplingを用いたモンテカルロ法に基づくタイミング歩留り解析の高速化
粟野皓光; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2017

動画のフレーム間相関を利用した圧縮センシングの高速復元手法
小西慧; 廣本正之; 佐藤高史
信学技報スマートインフォメディアシステム研究会, Mar. 2017

イジングモデルのソフトウェア実装による最大カット問題の求解性能評価
岡本浩尚; 業天英範; 廣本正之; 佐藤高史
電子情報通信学会総合大会, Mar. 2017

手の動画像からの心拍間隔推定に関する一検討
藤田雄也; 廣本正之; 佐藤高史
電子情報通信学会総合大会, Mar. 2017

演算簡略化手法評価のための畳み込みニューラルネットワークのFPGA実装
氏家隆之; 廣本正之; 佐藤高史
第42回パルテノン研究会, Dec. 2016

イジングモデルのFPGA実装による最大カット問題の求解速度評価
業天英範; 廣本正之; 佐藤高史
第42回パルテノン研究会, Dec. 2016

スイッチング波形を利用したパワーMOSFETの入力容量測定とモデル化
大石一輝; 新谷道広; 廣本正之; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Nov. 2016

Aging-aware Timing Analysis Based on Machine Learning
S. Bian; M. Shintani; M. Hiromoto; T. Sato
DA Symposium, Sep. 2016, Peer-reviewed

PWM電力制御によるパワーデバイスの熱伝達特性測定
大石一輝; 新谷道広; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会基礎・境界/NOLTA講演論文集, Sep. 2016

V溝構造SiCパワーMOSFETの静特性モデル化に関する一考察
新谷道広; 大石一輝; 周瑞; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会基礎・境界/NOLTA講演論文集, Sep. 2016

Binarized Neural Networkを用いた画像認識ハードウェアの消費エネルギー評価
三宅哲史; 氏家隆之; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会基礎・境界/NOLTA講演論文集, Sep. 2016

NBTIによるしきい値電圧変動のストレス確率依存性の評価
忻瑞徳; 森田俊平; 新谷道広; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会基礎・境界/NOLTA講演論文集, Sep. 2016

しきい値電圧ばらつきによるBistable Ring PUFの応答予測
田中悠貴; 吉永幹; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会基礎・境界/NOLTA講演論文集, Sep. 2016

顔と手の連続静止画からの脈波伝播時間推定に関する一検討
藤田雄也; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2016

ばらつきを考慮したメモリスタモデルによるニューラルネットワークの学習収束性の評価
山森聡; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会エレクトロニクス講演論文集2, Sep. 2016

有機トランジスタにおける漏れ電流特性のモデル化
齊藤成晃; 新谷道広; 小笠原泰弘; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会エレクトロニクス講演論文集2, Sep. 2016

表面ポテンシャルモデルを用いたSiCパワーMOSFETの過渡解析および昇圧回路への応用
奥田貴史; 中村洋平; 新谷道広; 佐藤高史; 引原隆士
電気学会産業応用部門大会(JIASC), Aug. 2016

零電圧スイッチング動作に基づくゲートドライバのための設計解析式の検討
新谷道広; 孫宇チョン; 関谷大雄; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Jul. 2016

近似的予測戦略に基づく畳み込みニューラルネットワークプロセッサの低電力化
氏家隆之; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

Worst-Delay Path Extraction in NBTI-Degraded Processors Based on Signal Probability Analysis
辺松; 新谷道広; 森田俊平; 粟野浩光; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

Fast Selection of Replacement Candidate for NBTI Mitigation Logic Based on Representative Path Extraction
森田俊平; 辺松; 新谷道広; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

パッケージの熱伝達特性推定に基づくパワーMOSFET自己発熱モデル
大石一輝; 新谷道広; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

Body Diode Model for SiC Power VDMOSFET Considering Gate-Voltage Dependence
周瑞; 新谷道広; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

粒子フィルタを用いた光電脈波信号からの運動時心拍数推定手法
藤田雄也; 廣本正之; 佐藤高史
回路とシステムワークショップ, May 2016, Peer-reviewed

最大カット問題の高速求解に向けた二次元イジングモデルのFPGA実装
業天英範; 廣本正之; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2016

格子状電極を用いたジェスチャ認識向け電界センサによる導電体位置推定精度の評価
岸野瞬士; 廣本正之; 佐藤高史
電子情報通信学会総合大会(於九州大学) 基礎・境界講演論文集, Mar. 2016

Sパラメータに基づく等価回路を利用したDC-DCコンバータの高周波ノイズモデリング
高垣勇登; 黒谷欣吾; 日高青路; 廣本正之; 佐藤高史
電気学会全国大会講演論文集, Mar. 2016

表面電位に基づくSiCパワーMOSFETモデルを用いたE級増幅器の回路シミュレーションに関する検討
新谷道広; 廣本正之; 佐藤高史
電気学会全国大会講演論文集, Mar. 2016

Fast Monte Carlo based timing yield calculation
粟野皓光; 佐藤高史
信学技報 VLSI設計技術研究会(デザインガイア), Dec. 2015

SiCパワーMOSFETにおける帰還容量の測定とモデル化
新谷道広; 中村洋平; 廣本正之; 引原隆士; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Dec. 2015

電荷基準モデルに基づく縦型SiCパワーMOSFETのトランジスタモデル
周瑞; 新谷道広; 廣本正之; 佐藤高史
電気学会研究会資料半導体電力変換研究会(SPC), Oct. 2015

粒子フィルタを用いた運動時ノイズに頑健な心拍数推定アルゴリズム
藤田雄也; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

二次元イジングモデルによる最大カット問題の求解における収束の早いスピン更新方法の検討
業天英範; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

プロセッサのNBTI劣化緩和法における劣化抑止制御回路の置換箇所削減に関する一検討
森田俊平; 辺松; 新谷道広; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

SiCパワーMOSFET寄生ダイオードのPN接合ダイオードモデルを用いたモデル化
大石一輝; 新谷道広; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

低電圧畳み込みニューラルネットワーク回路における演算誤り緩和に向けたプーリング手法の検討
氏家隆之; 大荷唯明; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

電荷基準モデルに基づく縦型SiCパワーMOSFETの電流特性モデル化の検討
周瑞; 新谷道広; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2015

Improved Pooling Method for Error Mitigation in Low-Voltage Convolutional Neural Network Circuits
Ujiie Takayuki; Oni Tadaaki; Hiromoto Masayuki; Sato Takashi
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference, 25 Aug. 2015

Fast Estimation on NBTI-induced Delay Degradation Based on Signal Probability
S. Bian; M. Shintani; M. Hiromoto; T. Sato
DA Symposium, Aug. 2015, Peer-reviewed

ばらつき考慮シミュレーションの最近の動向(招待)
佐藤高史
回路とシステムワークショップ, Aug. 2015, Peer-reviewed, Invited

圧縮センシング向けイメージセンサにおける省電力な観測行列生成回路
小西慧; 廣本正之; 佐藤高史
回路とシステムワークショップ, Aug. 2015, Peer-reviewed

ニューラルネットワークハードウェアの低電圧動作時における演算誤り緩和
大荷唯明; 廣本正之; 佐藤高史
回路とシステムワークショップ, Aug. 2015, Peer-reviewed

デバイス特性の経年劣化に起因する不良確率変化の効率的な解析手法
粟野皓光; 廣本正之; 佐藤高史
DA シンポジウム, Aug. 2015, Peer-reviewed

A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture
BIAN Song; SHINTANI Michihiro; WANG Zheng; HIROMOTO Masayuki; CHATTOPADHYAY Anupam; SATO Takashi
Technical report of IEICE. VLD, Mar. 2015

RTN起因のリングオシレータ発振周波数変動を利用したPUF
吉永幹; 粟野皓光; 廣本正之; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2015

パワーMOSFETデバイスモデルに向けた自動モデルパラメータ決定手法に関する一検討
新谷道広; 廣本正之; 佐藤高史
電気学会全国大会講演論文集, Mar. 2015

RTNを考慮したSRAM不良確率の高速計算
粟野皓光; 廣本正之; 佐藤高史
信学技報 VLD研究会(デザインガイア), Nov. 2014

ランダムテレグラフノイズを用いたチップ識別手法の一検討
吉永幹; 粟野皓光; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2014

フリップフロップの最小動作電圧計測のためのFPGAを用いた自動設計環境の構築
岡崎剛; 川島潤也; 廣本正之; 佐藤高史
第40回パルテノン研究会, Sep. 2014

粗粒度再構成可能アーキテクチャ向けの省メモリな耐ソフトエラー時間多重化手法
今川隆司; 廣本正之; 越智裕之; 佐藤高史
第40回パルテノン研究会, Sep. 2014

An Experimental Study on Interdigital Capacitance Sensor for Detecting Heart Rate
X. Cao; M. Hiromoto; T. Sato
Workshop on Circuits and Systems, Aug. 2014, Peer-reviewed

Failure-Region Exploration Using Steepest Descent Method for Accelerating High Dimensional Failure Rate Analysis
木村和紀; 廣本正之; 佐藤高史
回路とシステムワークショップ, Aug. 2014, Peer-reviewed

低電圧起動回路を用いた省電力チップ間非接触通信回路 (VLSI設計技術)
佐川善彦; 廣本正之; 佐藤高史; 越智裕之
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 29 May 2014

ランダムウォーク電源網解析の高速化に向けた節点解析順序の検討(回路・ゲートレベル,システム設計及び一般)
岡崎剛; 廣本正之; 佐藤高史
電子情報通信学会技術研究報告. VLD, VLSI設計技術, 22 May 2014

ランダムウォーク電源網解析の高速化に向けた節点解析順序の検討
岡崎剛; 廣本正之; 佐藤高史
情報処理学会SLDM研究会, May 2014

低電圧起動回路を用いた省電力チップ間非接触通信回路
佐川善彦; 廣本正之; 佐藤高史; 越智裕之
情報処理学会SLDM研究会, May 2014

最大動作周波数テストの枠組みを用いたデバイスパラメータ推定手法
新谷道弘; 佐藤高史
電子情報通信学会ディペンダブルコンピューティング研究会, Feb. 2014

3端子コンデンサにおける周波数特性の有理関数近似と等価回路表現
高垣勇登; 三舩洋嗣; 日高青路; 廣本正之; 佐藤高史
電子情報通信学会EMCJ研究会, Jan. 2014

Variable-Bitrate Compressive Sensing Using Total Variation Regularization
Dan Luo; Fujita Takafumi; Hiromoto Masayuki; Sato Takashi
Proceedings of the Society Conference of IEICE, 03 Sep. 2013

TV最適化を用いた可変レート圧縮センシング
羅丹; 藤田隆史; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会(於福岡工業大学), Sep. 2013

トランジスタアレイを用いたBTI劣化の統計的観測
粟野皓光; 佐藤高史
DA シンポジウム, Aug. 2013

3996トランジスタにおけるNBTI劣化の統計的ばらつき
粟野皓光; 廣本正之; 佐藤高史
DA シンポジウム, Aug. 2013

低電源電圧におけるフリップフロップの故障モードの解析
藤田隆史; 川島潤也; 廣本正之; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ICD研究会, Jul. 2013

SRAM 回路解析における最小ノルム不良サンプルと歩留りの関係
木村和紀; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013, Peer-reviewed

画像の圧縮センシングにおける圧縮率の適応的変更手法
藤田隆史; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013, Peer-reviewed

A Random Walk Based Power Supply Network Analysis utilizing Quasi Zero Variance Importance Sampling and Error Smoothing
岡崎剛; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013, Peer-reviewed

C-12-7 Comparison of energy consumption of latches of different topologies
Fujita Takafumi; Tsutsui Hiroshi; Ochi Hiroyuki; Sato Takashi
Proceedings of the IEICE General Conference, 05 Mar. 2013

Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation
SHINTANI Michihiro; SATO Takashi
Technical report of IEICE. VLD, 04 Mar. 2013

[Memorial Lecture] an Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani; T. Sato
IEICE Technical Report, Mar. 2013

Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
S. Zhang; H. Tsutsui; H. Ochi; T. Sato
IEICE general conference, Mar. 2013

オンラインテストを指向したIDDQ電流しきい値決定手法の検討
新谷道弘; 佐藤高史
電子情報通信学会VLSI設計技術研究会, Mar. 2013

A study on spatial frequency domain impedance matrix as a compact LSI multi-port model
森下拓海; 日高青路; 山長功; 佐藤高史
電子情報通信学会EMCJ研究会, Mar. 2013

回路構造の異なるラッチの消費エネルギーの比較
藤田隆史; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会総合大会(於岐阜大学) 基礎・境界講演論文集, Mar. 2013

ランダムウォーク線形回路解析のスレッド並列化における電圧源化排他制御の検討
岡崎剛; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会総合大会(於岐阜大学) 基礎・境界講演論文集, Mar. 2013

チップ試作による最小動作電圧予測手法の評価
川島潤也; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ICD研究会, Dec. 2012

Accurate I/O Buffer Impedance Self-adjustment Using Vth and Temperature Sensors
Z. Li; H. Tsutsui; H. Ochi; T. Sato
Design gaia, SLDM society conference, Nov. 2012

回路の最小動作電圧改善とその予測精度向上の一検討
川島潤也; 越智裕之; 筒井弘; 佐藤高史
回路とシステムワークショップ, Aug. 2012, Peer-reviewed

クリロフ部分空間法を用いた電源回路網解析の GPU 実装による高速化
森下拓海; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Aug. 2012, Peer-reviewed

情報量規準を用いる RTN モデルパラメータ推定の自動化
清水裕史; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2012

微細CMOSタイミング設計の新しいコーナー削減手法
小谷憲; 増田弘生; 成木保文; 奥村隆昌; 城間誠; 金本俊幾; 古川且洋; 山中俊輝; 小笠原泰弘; 佐藤高史; 橋本昌宜; 黒川敦; 田中正和
DA シンポジウム, Aug. 2012

微細プロセス(22nm世代)における配線コーナー削減手法の検討
城間誠; 山中俊輝; 小笠原泰弘; 金本俊幾; 成木保文; 奥村隆昌; 増田弘生; 古川且洋; 佐藤高史; 橋本昌宜; 黒川敦; 田中正和
DA シンポジウム, Aug. 2012

IDDQ 電流による大域プロセスばらつきの推定手法
新谷道広; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2012

低ESRと高ESRコンデンサの組み合わせ使用による電源インピーダンスの低減手法
山長功; 佐藤高史
エレクトロニクス実装学会全国大会, Mar. 2012

An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation
SHINTANI Michihiro; SATO Takashi
信学技報ディペンダブルコンピューティング研究会, Feb. 2012

ランダムテレグラフノイズモデル化のためのパラメータ推定法の検討
粟野皓光; 清水裕史; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

ゼロ分散推定重点的サンプリングを用いたランダムウォークによる過渡解析
宮川哲朗; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

ブロック反復法を用いた電源回路網解析の高速化
森下巧海; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

A Sensor-based Self-adjustment Approach for Controlling I/O Buffer Impedance
Z. Li; H. Tsutsui; H. Ochi; T. Sato
IEICE society conference, Sep. 2011

EM法によるMOSデバイス界面状態数の自動推定
清水裕史; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2011

ヤコビ法を用いた電源回路網解析の GPU 実装
森下巧海; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2011

A Design strategy for Subthreshold Circuits Considering Energy-Minimization and Yield-Maximization
川島潤也; 越智裕之; 筒井弘; 佐藤高史
回路とシステムワークショップ, Aug. 2011, Peer-reviewed

複数不良領域を持つ回路歩留まり解析のための逐次重点的サンプリング法
片山健太郎; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2011

配線資源の信頼性モデルを用いた粗粒度再構成可能アーキテクチャ向け選択的三重化の最適化手法
今川隆司; 湯浅洋史; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2011

CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析
佐方剛; 成木保文; 奥村隆昌; 金本俊幾; 増田弘生; 佐藤高史; 橋本昌宜; 古川且洋; 田中正和; 山中俊輝
DA シンポジウム, Aug. 2011

混合正規分布による重点的サンプリングの高次元ばらつき解析への適用
萩原汐; 伊達貴徳; 上薗巧; 益一哉; 佐藤高史
情報処理学会第148回システムLSI設計技術研究会, Mar. 2011

リングオシレータによるしきい値簡易測定の温度依存性の検討
上薗巧; 越智裕之; 佐藤高史
信学技報 VLSI設計技術研究会, Sep. 2010

Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architectures
YUASA Hiroshi; IMAGAWA Takashi; HIROMOTO Masayuki; OCHI Hiroyuki; SATO Takashi
IEICE technical report, May 2010

An efficient technique to search failure-areas for yield estimation via partial hypersphere
DATE Takanori; HAGIWARA Shiho; MASU Kazuya; SATO Takashi
IEICE technical report, Mar. 2010

重点的サンプリングにおける平均値移動量の決定手法とそのSRAM歩留り解析への適用
伊達貴徳; 萩原汐; 益一哉; 佐藤高史
情報処理学会第142回システムLSI設計技術研究会, Dec. 2009

セラミックコンデンサのモデル化とオンパッケージでの電源ノイズ対策
佐藤高史
シリコンRF研究会, Nov. 2009

パス遅延測定によるチップ特性の推定手法
高橋知之; 上薗巧; 越智裕之; 益一哉; 佐藤高史
DA シンポジウム, Aug. 2009

柔軟な信頼性を実現する再構成可能デバイスのための配置配線ツール
今川隆司; 廣本正之; 高永勲; Dawood Alnajjar; 密山幸男; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2009

RTNを考慮した回路特性ばらつき解析方法の検討
増田弘生; 佐方剛; 佐藤高史; 橋本昌宜; 古川且洋; 田中正和; 山中俊輝; 金本俊幾
DA シンポジウム, Aug. 2009

重点的サンプリングを用いたランダムウォークによる線形回路解析の高速化
宮川哲朗; 山長功; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2009

Importance sampling with two-phase preprocess considering structural symmetry of SRAM circuits
DATE Takanori; HAGIWARA Shiho; UEZONO Takumi; SATO Takashi; MASU Kazuya
IEICE technical report, May 2009

電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法
榎並孝司; 橋本昌宜; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2009

適応型テストにおけるクリティカルパスのクラスタリング手法
上薗巧; 高橋知之; 植山寛之; 新谷道広; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2009

統計的タイミング情報に基づく適応型テスト
新谷道広; 高橋知之; 植山寛之; 上薗巧; 佐藤高史; 畠山一実; 相京隆; 益一哉
電子情報通信学会総合大会, Mar. 2009

Calculation of State-Dependent Power-Distribution-Network Capacitance Based on Table Look Up
Yamanaga Koh; Takahashi Ryo; Hagiwara Shiho; Sato Takashi; Masu Kazuya
電子情報通信学会総合大会, Mar. 2009

A Study on Power-supply Capacitance Model Considering State Dependency
Hagiwara Shiho; Takahashi Ryo; Yamanaga Koh; Sato Takashi; Masu Kazuya
電子情報通信学会総合大会, Mar. 2009

STIストレスによるMOSFET特性変動のコンパクトモデル
山田健太; 庄俊之; 益一哉; 中山範明; 佐藤高史; 天川修平; 國清辰也; 吉村尚郎; 伊藤優; 熊代成孝
第56回応用物理学関係連合講演会, Mar. 2009

CMOS論理回路における電源網容量の入力状態依存性についての検討
高橋亮; 山長功; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

電源電圧変動やプロセスばらつきに対する標準セルの遅延感度検討
高橋知之; 植山寛之; 萩原汐; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

抵抗測定法によるトランジスタアレイ回路の測定時間短縮化
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

回路特性ばらつき解析に対する重点的サンプリングの適用検討
伊達貴徳; 萩原汐; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

LSI等価回路モデル評価に向けたオンチップ電源電圧の測定手法
佐藤高史; 山長功
電子情報通信学会ソサイエティ大会, Sep. 2008

パス遅延時間ばらつきを考慮した電源遮断回路の設計指針
萩原汐; 佐藤高史; 益一哉
DA シンポジウム, Aug. 2008

プロセスばらつきの積極的活用による非繰返し電圧波形の測定
上薗巧; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

電源遮断回路におけるパス遅延時間ばらつきの計算
萩原汐; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

基板実装状態を考慮可能な表面実装型受動部品の2ポートモデリング手法
山長功; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

チップ内システマティックばらつきと回路スキュー特性相関
増田弘生; 大川眞一; 黄田剛; 奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任
第21回回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案
奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任
第21回回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

リーク電流測定用トランジスタアレイ回路の測定
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会総合大会, Mar. 2008

測定系の侵襲性を定量化可能なオンチップ電源電圧変動の直接測定手法
山長功; 佐藤; 高史; 益一哉
電子情報通信学会総合大会, Mar. 2008

電源遮断回路におけるインバータ列遅延時間ばらつきの計算
萩原汐; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2008

[チュートリアル講演] 集積回路における電源品質の解析技術
佐藤高史
信学技報, Jan. 2008

プリント配線基板電源網のインピーダンス低減手法の検討
山長功; 佐藤高史; 益一哉
システムLSIワークショップ, Nov. 2007

Full-wave 電磁界シミュレータによるプリント回路基板の電源網モデル化
山長功; 佐藤高史; 益一哉
シリコンRF研究会, Nov. 2007

パワーゲーティング技術における製造ばらつきの回路特性への影響
萩原汐; 佐藤高史; 益一哉
情報処理学会第131回システムLSI設計技術研究会, Oct. 2007

An Implementation of Voltage Drop Sensor Circuit for Power Supply Network Monitoring
T. Sato; T. Uezono; K. Masu
Workshop on SoC Design Methodologies, Sep. 2007

ビアのインダクタンスに着目したプリント配線基板電源網のインピーダンス低減手法の検討
山長功; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

電源電圧降下の時間的・空間的広がり可視化手法
上薗巧; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

大域ばらつきの近似次数が回路遅延ばらつきに与える影響
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

ノンパラメトリック統計的タイミング解析 (SSTA) の実現手法の検討
今井正紀; 佐藤高史; 中山範明; 益一哉
DA シンポジウム, Aug. 2007

相関係数にもとづく回帰分析の電源改善への適用
萩原汐; 上薗巧; 佐藤高史; 益一哉
第20回回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

45-65nm ノードにおける遅延ばらつき特性の環境温度依存性
中林太美世; 黒川敦; 佐藤高史; 橋本昌宜; 増田弘生
第20回回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

統計的パス遅延解析のための Monte Carlo STA 実行数評価の一手法
今井正紀; 佐藤高史; 中山範明; 益一哉
第20回回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案
高藤浩資; 小林宏行; 小野信任; 増田弘生; 中島英斉; 奥村隆昌; 橋本昌宜; 佐藤高史
第20回回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

電源解析への相関係数利用の検討
萩原汐; 上薗巧; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2007

非理想的な回路分割とセル占有率を考慮した配線長分布モデル
天川修平; 上薗巧; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2007

電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現
小笠原泰弘; 榎並孝司; 橋本昌宜; 佐藤高史; 尾上孝雄
信学技報, Jan. 2007

MOSFETのリーク電流ばらつき測定のための回路検討
藤久雄己; 岡田健一; 佐藤高史; 中山範明; 益一哉
システムLSIワークショップ, Nov. 2006

高精度デバイスばらつき測定のための電源構造の設計
萩原汐; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

リングオシレータを用いる瞬時電圧降下測定手法の精度改善
上薗巧; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

伝送線路を用いたオンチップ高速伝送回路の研究
清田淳紀; 伊藤浩之; 岡田健一; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

Si CMOSチップにおける右手・左手系伝送線路の検討
金章九; 山内拓弥; 岡田健一; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

MOSFETのリーク電流ばらつき測定のための回路検討
藤久雄己; 上園巧; 萩原汐; 岡田健一; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

統計的 STA の精度検証手法
小林宏行; 小野信任; 佐藤高史; 岩井二郎; 橋本昌宜
DA シンポジウム, Jul. 2006

統計的 SSTA の精度検証方法
小林宏行; 小野信任; 佐藤高史; 岩井二郎; 橋本昌宜
第19回回路とシステム軽井沢ワークショップ, Apr. 2006, Peer-reviewed

オンチップ熱バラツキを考慮したモジュール配置手法
岡田典英; 児玉親亮; 佐藤高史; 藤吉邦洋
DA シンポジウム, Aug. 2005

ジッタ制約を考慮した IO 同時動作設計ルールの提案
蜂屋孝太郎; 小林宏行; 奥村隆昌; 佐藤高史; 岡宏規
第18回回路とシステム軽井沢ワークショップ, Apr. 2005, Peer-reviewed

フロアプランにおけるオンチップ熱ばらつきの解析と対策
佐藤高史; 市宮淳次; 小野信任; 蜂屋孝太郎; 橋本昌宜
DA シンポジウム, Jul. 2004

オンチップ・インダクタンスとは? --モデリングと抽出技術--
黒川敦; 佐藤高史; 金本俊幾
DA シンポジウム, Jul. 2003

VLSI 設計・信号品質解析におけるインダクタンスの影響とその重要性
佐藤高史; 金本俊幾; 黒川敦
DA シンポジウム, Jul. 2003

電源・グランド間容量が同時切替えノイズに与える影響の解析
坂田和之; 佐藤高史; 横溝剛一
第17回回路とシステム(軽井沢)ワークショップ, Apr. 2003

インダクタンスに起因する配線遅延変動の統計的予測手法
佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
電子情報通信学会ソサイエティ大会チュートリアル講演, Sep. 2002

0.1-um級 LSI の遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法
金本俊幾; 佐藤高史; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
DA シンポジウム, Jul. 2002

動的電源ノイズ解析のための電源グリッドモデル抽出
蜂屋孝太郎; 黒川敦; 佐藤高史; 南文裕; 増田弘生
DAシンポジウム, Jul. 2002

斜め配線を含む VLSIの高速オンチップ・インダクタンス解析
黒川敦; 蜂屋孝太郎; 佐藤高史; 徳升一也; 増田弘生
第15回回路とシステム(軽井沢)ワークショップ, Apr. 2002, Peer-reviewed

インダクタンスが配線遅延に及ぼす影響の定量的評価方法
佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
第15回回路とシステム(軽井沢)ワークショップ, Apr. 2002, Peer-reviewed

有限要素法と回路解析の連成解析による同時切替えノイズの評価
馬淵雄一; 諏訪元大; 中村篤; 福本英士; 白井優之; 林亨; 横溝剛一; 佐藤高史; 大竹成典; 坂田和之
第14回エレクトロニクス実装学会全国大会, Mar. 2002

クロストークノイズによる配線遅延の変動とノイズ波形のモデル化に関する検討
Takashi Sato; Yu Cao; Dennis Sylvester; Chenming Hu
信学技報, Sep. 2000

LSI model to simulate High Frequency Current on Printed Circuit Board
OHTAKE Shigenori; MABUCHI Yuichi; HAYASHI Tohru; SATO Takashi; YOKOMIZO Gohichi; SHIRAKAWA Shinji; FUKUMOTO Hideshi; NAKAMURA Atsushi
IEICE technical report. Electromagnetic compatibility, Jul. 2000

5GByte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM
SATO Takashi; NISHIO Yoji; SUGANO Toshio; NAKAGOME Yoshinobu
IEICE technical report. Electron devices, Jun. 1998

A Practical Row Interchanging Algorithm for Hierarchically Constructed Circuit Matrices using Modified Nodal Analysis
SATO Takashi; MIYAMA Mikako; YOKOMIZO Goichi; NIHO Kojiro
Technical report of IEICE. VLD, Dec. 1997

メモリ回路を用いた回路分割型回路シミュレーションの評価
見山美可子; 佐藤高史; 北城三郎; 仁保宏二郎
信学技報, Apr. 1996

機能関数を用いたアナログ/デジタル混在回路機能検証高速化手法の一検討
佐藤高史; 信澤理子; 見山美可子; 横溝剛一
電子情報通信学会総合大会, Mar. 1994

Presentations

ランダムテレグラフノイズを用いたチップ識別手法の一検討
吉永幹; 粟野皓光; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2014

フリップフロップの最小動作電圧計測のためのFPGAを用いた自動設計環境の構築
岡崎剛; 川島潤也; 廣本正之; 佐藤高史
第40回パルテノン研究会, Sep. 2014

粗粒度再構成可能アーキテクチャ向けの省メモリな耐ソフトエラー時間多重化手法
今川隆司; 廣本正之; 越智裕之; 佐藤高史
第40回パルテノン研究会, Sep. 2014

An Experimental Study on Interdigital Capacitance Sensor for Detecting Heart Rate
X. Cao; M. Hiromoto; T. Sato
Workshop on Circuits and Systems, Aug. 2014

高次元回路歩留まり解析高速化のための最急降下法を用いた不良領域探索
木村和紀; 廣本正之; 佐藤高史
回路とシステムワークショップ, Aug. 2014

A Low Cost Capacitor Approach for Suppressing Resonance in Power Distribution Networks
K. Yamanaga; H. Yamamoto; T. Sato
International Symposium on Electromagnetic Compatibility, Tokyo (EMC Tokyo), May 2014

ランダムウォーク電源網解析の高速化に向けた節点解析順序の検討
岡崎剛; 廣本正之; 佐藤高史
情報処理学会SLDM研究会, May 2014

低電圧起動回路を用いた省電力チップ間非接触通信回路
佐川善彦; 廣本正之; 佐藤高史; 越智裕之
情報処理学会SLDM研究会, May 2014

Experimental Validation of Minimum Operating Voltage Estimation for Low Supply Voltage Circuits
T. Sato; J. Kawashima; H. Tsutsui; H. Ochi
International Symposium on Quality Electronic Design (ISQED), Mar. 2014

最大動作周波数テストの枠組みを用いたデバイスパラメータ推定手法
新谷道弘; 佐藤高史
電子情報通信学会ディペンダブルコンピューティング研究会, Feb. 2014

3端子コンデンサにおける周波数特性の有理関数近似と等価回路表現
高垣勇登; 三舩洋嗣; 日高青路; 廣本正之; 佐藤高史
電子情報通信学会EMCJ研究会, Jan. 2014

Time Dependent Degradation (Invited)
T. Sato; M. Hashimoto
The Journal of Reliability Engineering Association of Japan, Dec. 2013, Invited

Statistical Observation of NBTI and PBTI Degradations
H. Awano; M. Hiromoto; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2013

A Device Array for Flexible BTI Characterization (Invited Talk)
T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2013

Place-and-route Algorithms for a Reliability-oriented Coarse-grained Reconfigurable Architecture Using Time Redundancy
T. Imagawa; M. Hiromoto; H. Tsutsui; H. Ochi; T. Sato
The 18th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2013

Statistical Simulation Methods for Analyzing Performance of Low Supply Voltage Circuits (Invited)
T. Sato
The IEEE 10th International Conference on ASIC (ASICON), Sep. 2013, Invited

TV最適化を用いた可変レート圧縮センシング
羅丹; 藤田隆史; 廣本正之; 佐藤高史
電子情報通信学会ソサイエティ大会(於福岡工業大学), Sep. 2013

トランジスタアレイを用いたBTI劣化の統計的観測
粟野皓光; 佐藤高史
DA シンポジウム, Aug. 2013

3996トランジスタにおけるNBTI劣化の統計的ばらつき
粟野皓光; 廣本正之; 佐藤高史
DA シンポジウム, Aug. 2013

低電源電圧におけるフリップフロップの故障モードの解析
藤田隆史; 川島潤也; 廣本正之; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ICD研究会, Jul. 2013

SRAM 回路解析における最小ノルム不良サンプルと歩留りの関係
木村和紀; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013

画像の圧縮センシングにおける圧縮率の適応的変更手法
藤田隆史; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013

準ゼロ分散推定と誤差平滑化処理を併用するランダムウォーク電源網解析
岡崎剛; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Jul. 2013

Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
S. Zhang; H. Tsutsui; H. Ochi; T. Sato
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jun. 2013

Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
S. Matsuda; T. Imagawa; H. Tsutsui; T. Sato; Y. Nakamura; H. Ochi
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jun. 2013

Fast and Memory-efficient GPU Implementations of Krylov Subspace Methods for Efficient Power Grid Analysis
T. Morishita; H. Tsutsui; H. Ochi; T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013

Logarithmic Modeling of BTI Under Dynamic Circuit Operations: Static, Dynamic and Long-term Prediction
J. B. Velamala; K. B. Sutaria; H. Shimizu; H. Awano; T. Sato; G. Wirth; Y. Cao
IEEE International Reliability Physics Symposium (IRPS), Apr. 2013

Multi-trap RTN Parameter Extraction Based on Bayesian Inference
H. Awano; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2013

High-speed DFG-level SEU Vulnerability Analysis for Applying Selective TMR to Resource-constrained CGRA
T. Imagawa; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2013

[Memorial Lecture] an Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani; T. Sato
IEICE Technical Report, Mar. 2013

Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
S. Zhang; H. Tsutsui; H. Ochi; T. Sato
IEICE general conference, Mar. 2013

Hot-swapping Architecture With Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array
Z. E. Rakossy; M. Hiromoto; H. Tsutsui; T. Sato; Y. Nakamura; H. Ochi
Design, Automation and Test in Europe (DATE), Mar. 2013

A Cost-effective Selective TMR for Heterogeneous Coarse-grained Reconfigurable Architectures Based on DFG-level Vulnerability Analysis
T. Imagawa; H. Tsutsui; H. Ochi; T. Sato
Design, Automation and Test in Europe (DATE), Mar. 2013

オンラインテストを指向したIDDQ電流しきい値決定手法の検討
新谷道弘; 佐藤高史
電子情報通信学会VLSI設計技術研究会, Mar. 2013

空間周波数領域インピーダンス行列を用いたマルチポートLSIモデルの検討
森下拓海; 日高青路; 山長功; 佐藤高史
電子情報通信学会EMCJ研究会, Mar. 2013

回路構造の異なるラッチの消費エネルギーの比較
藤田隆史; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会総合大会(於岐阜大学) 基礎・境界講演論文集, Mar. 2013

ランダムウォーク線形回路解析のスレッド並列化における電圧源化排他制御の検討
岡崎剛; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会総合大会(於岐阜大学) 基礎・境界講演論文集, Mar. 2013

Realization of Frequency-domain Circuit Analysis Through Random Walk
T. Miyakawa; H. Tsutsui; H. Ochi; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013

An Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani; T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013

チップ試作による最小動作電圧予測手法の評価
川島潤也; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ICD研究会, Dec. 2012

Adaptive Current-threshold Determination for Accurate IDDQ Testing
M. Shintani; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2012

Accurate I/O Buffer Impedance Self-adjustment Using Vth and Temperature Sensors
Z. Li; H. Tsutsui; H. Ochi; T. Sato
Design gaia, SLDM society conference, Nov. 2012

The Odd Couple: Antiresonance Control by Two Capacitors of Unequal Series Resistances
K. Yamanaga; T. Sato
The 21st conference on electrical performance of electronic packaging and systems (EPEPS), Oct. 2012

Statistical Aging Under Dynamic Voltage Scaling: A Logarithmic Model Approach
J. B. Velamala; K. B. Sutaria; H. Shimizu; H. Awano; T. Sato; Y. Cao
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2012

回路の最小動作電圧改善とその予測精度向上の一検討
川島潤也; 越智裕之; 筒井弘; 佐藤高史
回路とシステムワークショップ, Aug. 2012

クリロフ部分空間法を用いた電源回路網解析の GPU 実装による高速化
森下拓海; 筒井弘; 越智裕之; 佐藤高史
回路とシステムワークショップ, Aug. 2012

情報量規準を用いる RTN モデルパラメータ推定の自動化
清水裕史; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2012

微細CMOSタイミング設計の新しいコーナー削減手法
小谷憲; 増田弘生; 成木保文; 奥村隆昌; 城間誠; 金本俊幾; 古川且洋; 山中俊輝; 小笠原泰弘; 佐藤高史; 橋本昌宜; 黒川敦; 田中正和
DA シンポジウム, Aug. 2012

微細プロセス(22nm世代)における配線コーナー削減手法の検討
城間誠; 山中俊輝; 小笠原泰弘; 金本俊幾; 成木保文; 奥村隆昌; 増田弘生; 古川且洋; 佐藤高史; 橋本昌宜; 黒川敦; 田中正和
DA シンポジウム, Aug. 2012

Physics Matters: Statistical Aging Prediction Under Trapping/detrapping
J. B. Velamala; K. B. Sutaria; T. Sato; Y. Cao
ACM/IEEE Design Automation Conference (DAC), Jun. 2012

Aging Statistics Based on Trapping/detrapping: Silicon Evidence, Modeling and Long-term Prediction
J. B. Velamala; K. B. Sutaria; T. Sato; Y. Cao
IEEE International Reliability Physics Symposium (IRPS), Apr. 2012

A Bayesian-based Process Parameter Estimation Using IDDQ Current Signature
M. Shintani; T. Sato
IEEE VLSI Test Symposium (VTS), Apr. 2012

Hardware Architecture for Accelerating Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2012

GPU Acceleration of Cycle-based Soft-error Simulation for Reconfigurable Array Architectures
T. Imagawa; T. Oue; H. Tsutsui; H. Ochi; T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI), Mar. 2012

Statistical Observations of NBTI-induced Threshold Voltage Shifts on Small Channel-area Devices
T. Sato; H. Awano; H. Shimizu; H. Tsutsui; H. Ochi
International Symposium on Quality Electronic Design (ISQED), Mar. 2012

IDDQ 電流による大域プロセスばらつきの推定手法
新谷道広; 佐藤高史
信学技報 VLSI設計技術研究会, Mar. 2012

低ESRと高ESRコンデンサの組み合わせ使用による電源インピーダンスの低減手法
山長功; 佐藤高史
エレクトロニクス実装学会全国大会, Mar. 2012

プロセスばらつき推定に基づくIDDQテスト良品判定基準決定の試み
新谷道広; 佐藤高史
信学技報ディペンダブルコンピューティング研究会, Feb. 2012

Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Jan. 2012

Getting the Most Out of IDDQ Testing
M. Shintani; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2011

Statistical Aging Prediction and Characterization Using Trapping/detrapping Based NBTI Models
J. B. Velamala; T. Sato; Y. Cao
Workshop on variability modeling and characterization (VMC), Nov. 2011

ランダムテレグラフノイズモデル化のためのパラメータ推定法の検討
粟野皓光; 清水裕史; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

ゼロ分散推定重点的サンプリングを用いたランダムウォークによる過渡解析
宮川哲朗; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

ブロック反復法を用いた電源回路網解析の高速化
森下巧海; 筒井弘; 越智裕之; 佐藤高史
デザインガイア情報処理学会 SLDM研究会, Nov. 2011

A Device Array for Efficient Bias-temperature Instability Measurements
T. Sato; T. Kozaki; T. Uezono; H. Tsutsui; H. Ochi
Solid-State Device Research Conference (ESSDERC), Sep. 2011

A Design Strategy for Sub-threshold Circuits Considering Energy-minimization and Yield-maximization
J. Kawashima; H. Tsutsui; H. Ochi; T. Sato
IEEE International SOC Conference (SOCC), Sep. 2011

A Sensor-based Self-adjustment Approach for Controlling I/O Buffer Impedance
Z. Li; H. Tsutsui; H. Ochi; T. Sato
IEICE society conference, Sep. 2011

EM法によるMOSデバイス界面状態数の自動推定
清水裕史; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2011

ヤコビ法を用いた電源回路網解析の GPU 実装
森下巧海; 筒井弘; 越智裕之; 佐藤高史
電子情報通信学会ソサイエティ大会, Sep. 2011

エネルギー最小化と動作保証を考慮したサブスレッショルド回路の設計指針の検討
川島潤也; 越智裕之; 筒井弘; 佐藤高史
回路とシステムワークショップ, Aug. 2011

複数不良領域を持つ回路歩留まり解析のための逐次重点的サンプリング法
片山健太郎; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2011

配線資源の信頼性モデルを用いた粗粒度再構成可能アーキテクチャ向け選択的三重化の最適化手法
今川隆司; 湯浅洋史; 筒井弘; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2011

CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析
佐方剛; 成木保文; 奥村隆昌; 金本俊幾; 増田弘生; 佐藤高史; 橋本昌宜; 古川且洋; 田中正和; 山中俊輝
DA シンポジウム, Aug. 2011

A Stress-parallelized Device Array for Efficient Bias-temperature Stability Measurement
T. Sato; T. Kozaki; T. Uezono; H. Tsutsui; H. Ochi
The 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y), Jun. 2011

Acceleration of Random-walk-based Linear Circuit Analysis Using Importance Sampling
T. Miyakawa; K. Yamanaga; H. Tsutsui; H. Ochi; T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2011

A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs
H. Yuasa; H. Tsutsui; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2011

混合正規分布による重点的サンプリングの高次元ばらつき解析への適用
萩原汐; 伊達貴徳; 上薗巧; 益一哉; 佐藤高史
情報処理学会第148回システムLSI設計技術研究会, Mar. 2011

Sequential Importance Sampling for Low-probability and High-dimensional SRAM Yield Analysis
K. Katayama; S. Hagiwara; H. Tsutsui; H. Ochi; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010

A Transistor-array for Parallel BTI-effects Measurements
T. Uezono; T. Kozaki; H. Ochi; T. Sato
Workshop on variability modeling and characterization (VMC), Nov. 2010

リングオシレータによるしきい値簡易測定の温度依存性の検討
上薗巧; 越智裕之; 佐藤高史
信学技報, Sep. 2010

A Tool Chain for Generating SEU-vulnerability Map for Coarse-grained Reconfigurable Architecture
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
The 25th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jul. 2010

A Routing Architecture Exploration for Coarse-grained Reconfigurable Architecture With Automated SEU-tolerance Evaluation
T. Imagawa; M. Hiromoto; H. Ochi; T. Sato
IEEE International SOC Conference (SOCC), Jul. 2010

Application of Generalized Scattering Matrix for Prediction of Power Supply Noise
K. Yamanaga; K. Masu; T. Sato
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Jun. 2010

Decomposition of Drain-current Variation Into Gain-factor and Threshold Voltage Variations
T. Sato; T. Uezono; N. Nakayama; K. Masu
IEEE International Symposium on Circuits and Systems (ISCAS), May 2010

Small Delay and Area Overhead Process Parameter Estimation Through Path-delay Inequalities
T. Uezono; T. Takahashi; M. Shintani; K. Hatayama; K. Masu; H. Ochi; T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS), May 2010

誤り伝播に着目した粗粒度再構成可能アーキテクチャ向け部分的三重化手法
湯浅洋史; 今川隆司; 廣本正之; 越智裕之; 佐藤高史
信学技報, May 2010

Path Clustering for Adaptive Test
T. Uezono; T. Takahashi; M. Shintani; K. Hatayama; K. Masu; H. Ochi; T. Sato
IEEE VLSI Test Symposium (VTS), Apr. 2010

Sequential Importance Sampling for Low-probability and High-dimensional SRAM Yield Analysis
K. Katayama; T. Date; H. Ochi; T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Mar. 2010

Robust Importance Sampling for Efficient SRAM Yield Analysis
T. Date; S. Hagiwara; K. Masu; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2010

Linear Time Calculation of State-dependent Power Distribution Network Capacitance
S. Hagiwara; K. Yamanaga; R. Takahashi; K. Masu; H. Ochi; T. Sato
International Symposium on Quality Electronic Design (ISQED), Mar. 2010

超球の一部を用いた歩留まり推定における不良領域の効率的探索手法
伊達貴徳; 萩原汐; 益一哉; 佐藤高史
信学技報, Mar. 2010

重点的サンプリングにおける平均値移動量の決定手法とそのSRAM歩留り解析への適用
伊達貴徳; 萩原汐; 益一哉; 佐藤高史
情報処理学会第142回システムLSI設計技術研究会, Dec. 2009

On-die Parameter Extraction from Path-delay Measurements
T. Takahashi; T. Uezono; M. Shintani; K. Masu; T. Sato
IEEE Asian solid-state circuit conference (ASSCC), Nov. 2009

セラミックコンデンサのモデル化とオンパッケージでの電源ノイズ対策
佐藤高史
シリコンRF研究会, Nov. 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information
M. Shintani; T. Uezono; T. Takahashi; H. Ueyama; T. Sato; K. Hatayama; T. Aikyo; K. Masu
IEEE Asian Test Symposium (ATS), Sep. 2009

パス遅延測定によるチップ特性の推定手法
高橋知之; 上薗巧; 越智裕之; 益一哉; 佐藤高史
DA シンポジウム, Aug. 2009

柔軟な信頼性を実現する再構成可能デバイスのための配置配線ツール
今川隆司; 廣本正之; 高永勲; Dawood Alnajjar; 密山幸男; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2009

RTNを考慮した回路特性ばらつき解析方法の検討
増田弘生; 佐方剛; 佐藤高史; 橋本昌宜; 古川且洋; 田中正和; 山中俊輝; 金本俊幾
DA シンポジウム, Aug. 2009

重点的サンプリングを用いたランダムウォークによる線形回路解析の高速化
宮川哲朗; 山長功; 越智裕之; 佐藤高史
DA シンポジウム, Aug. 2009

Bridging the Gap Between Laboratory Measurement and Simulation Model (Invited)
T. Sato
International Workshop on Emerging Circuits and Systems (IWECS), Jul. 2009, Invited

Two-dimensional Moment Method for Analyzing Current Distribution of a Ceramic Capacitor
K. Yamanaga; S. Amakawa; T. Sato; K. Masu
International Symposium on Electromagnetic Compatibility (EMC Kyoto), Jul. 2009

Application of the EMI Decoupling Circuit Consisting of Two Capacitors and a Power Trace to Quad Flat Package (QFP) LSI
H. Sasaki; T. Harada; T. Kuriyama; T. Sato; K. Masu
IEICE Transactions on Communications (Japanese Edition), May 2009

SRAM回路の構造的対称性を考慮した2段階学習型重点的サンプリング
伊達貴徳; 萩原汐; 上薗巧; 佐藤高史
信学技報, May 2009

S-parameter-based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-embedding
S. Amakawa; K. Yamanaga; H. Ito; T. Sato; N. Ishihara; K. Masu
IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar. 2009

電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法
榎並孝司; 橋本昌宜; 佐藤高史
信学技報o, Mar. 2009

適応型テストにおけるクリティカルパスのクラスタリング手法
上薗巧; 高橋知之; 植山寛之; 新谷道広; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2009

統計的タイミング情報に基づく適応型テスト
新谷道広; 高橋知之; 植山寛之; 上薗巧; 佐藤高史; 畠山一実; 相京隆; 益一哉
電子情報通信学会総合大会, Mar. 2009

状態依存性解析のための電源間容量のテーブルルックアップ計算
山長功; 高橋亮; 萩原汐; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2009

状態依存性を考慮した論理回路の電源間容量モデルの検討
萩原汐; 高橋亮; 山長功; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2009

STIストレスによるMOSFET特性変動のコンパクトモデル
山田健太; 庄俊之; 益一哉; 中山範明; 佐藤高史; 天川修平; 國清辰也; 吉村尚郎; 伊藤優; 熊代成孝
第56回応用物理学関係連合講演会, Mar. 2009

A MOS Transistor Array With Pico-ampere Order Precision for Accurate Characterization of Leakage Current Variation
T. Sato; H. Ueyama; N. Nakayama; K. Masu
IEEE Asian solid-state circuit conference (ASSCC), Nov. 2008

Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis
T. Enami; M. Hashimoto; T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2008

An Efficient Extraction of Random and Systematic Gate-length Variation Through Poly-Si Resistor Measurement
N. Nakayama; T. Sato; H. Ueyama; K. Masu
Workshop on Test Structure Design for Variability Characterization, Nov. 2008

Non-invasive Direct Probing for On-chip Voltage Measurement
T. Sato; K. Yamanaga; K. Masu
International SoC Design Conference (ISOCC), Nov. 2008

Accurate Parasitic Inductance Determination of a Ceramic Capacitor Through 2-port Measurements
K. Yamanaga; T. Sato; K. Masu
The 17th topical meeting on electrical performance of electronic packaging (EPEP), Oct. 2008

CMOS論理回路における電源網容量の入力状態依存性についての検討
高橋亮; 山長功; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

電源電圧変動やプロセスばらつきに対する標準セルの遅延感度検討
高橋知之; 植山寛之; 萩原汐; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

抵抗測定法によるトランジスタアレイ回路の測定時間短縮化
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

回路特性ばらつき解析に対する重点的サンプリングの適用検討
伊達貴徳; 萩原汐; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2008

LSI等価回路モデル評価に向けたオンチップ電源電圧の測定手法
佐藤高史; 山長功
電子情報通信学会ソサイエティ大会, Sep. 2008

パス遅延時間ばらつきを考慮した電源遮断回路の設計指針
萩原汐; 佐藤高史; 益一哉
DA シンポジウム, Aug. 2008

Non-parametric Statistical Static Timing Analysis: An SSTA Framework for Arbitrary Distribution
M. Imai; T. Sato; N. Nakayama; K. Masu
ACM/IEEE Design Automation Conference (DAC), Jun. 2008

On-chip Differential and Common Mode Voltage Measurement Using Off-chip Referenced Twin Probing
K. Yamanaga; T. Sato; K. Masu
IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2008

Substrate-geometry Aware 2-port Modeling for Surface-mount Passive Components
K. Yamanaga; T. Sato; K. Masu
19th International Zurich Symposium on Electromagnetic Compatibility, May 2008

プロセスばらつきの積極的活用による非繰返し電圧波形の測定
上薗巧; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008

電源遮断回路におけるパス遅延時間ばらつきの計算
萩原汐; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008

基板実装状態を考慮可能な表面実装型受動部品の2ポートモデリング手法
山長功; 佐藤高史; 益一哉
第21回回路とシステム軽井沢ワークショップ, Apr. 2008

チップ内システマティックばらつきと回路スキュー特性相関
増田弘生; 大川眞一; 黄田剛; 奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任
第21回回路とシステム軽井沢ワークショップ, Apr. 2008

統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案
奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任
第21回回路とシステム軽井沢ワークショップ, Apr. 2008

リーク電流測定用トランジスタアレイ回路の測定
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会総合大会, Mar. 2008

測定系の侵襲性を定量化可能なオンチップ電源電圧変動の直接測定手法
山長功; 佐藤; 高史; 益一哉
電子情報通信学会総合大会, Mar. 2008

電源遮断回路におけるインバータ列遅延時間ばらつきの計算
萩原汐; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2008

Determination of Optimal Polynomial Regression Function to Decompose On-die Systematic and Random Variations
T. Sato; H. Ueyama; N. Nakayama; K. Masu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2008

[チュートリアル講演] 集積回路における電源品質の解析技術
佐藤高史
信学技報, Jan. 2008

プリント配線基板電源網のインピーダンス低減手法の検討
山長功; 佐藤高史; 益一哉
システムLSIワークショップ, Nov. 2007

Full-wave 電磁界シミュレータによるプリント回路基板の電源網モデル化
山長功; 佐藤高史; 益一哉
シリコンRF研究会, Nov. 2007

A Study on Variation-component Decomposition Using Polynomial Smoothing Function
T. Sato; H. Ueyama; N. Nakayama; K. Masu
The 14th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2007

パワーゲーティング技術における製造ばらつきの回路特性への影響
萩原汐; 佐藤高史; 益一哉
情報処理学会第131回システムLSI設計技術研究会, Oct. 2007

Weakness Identification for Effective Repair of Power Distribution Network
T. Sato; S. Hagiwara; T. Uezono; K. Masu
17th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 2007

An Implementation of Voltage Drop Sensor Circuit for Power Supply Network Monitoring
T. Sato; T. Uezono; K. Masu
Workshop on SoC Design Methodologies, Sep. 2007

ビアのインダクタンスに着目したプリント配線基板電源網のインピーダンス低減手法の検討
山長功; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

電源電圧降下の時間的・空間的広がり可視化手法
上薗巧; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

大域ばらつきの近似次数が回路遅延ばらつきに与える影響
植山寛之; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2007

ノンパラメトリック統計的タイミング解析 (SSTA) の実現手法の検討
今井正紀; 佐藤高史; 中山範明; 益一哉
DA シンポジウム, Aug. 2007

相関係数にもとづく回帰分析の電源改善への適用
萩原汐; 上薗巧; 佐藤高史; 益一哉
第20回回路とシステム軽井沢ワークショップ, Apr. 2007

45-65nm ノードにおける遅延ばらつき特性の環境温度依存性
中林太美世; 黒川敦; 佐藤高史; 橋本昌宜; 増田弘生
第20回回路とシステム軽井沢ワークショップ, Apr. 2007

統計的パス遅延解析のための Monte Carlo STA 実行数評価の一手法
今井正紀; 佐藤高史; 中山範明; 益一哉
第20回回路とシステム軽井沢ワークショップ, Apr. 2007

統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案
高藤浩資; 小林宏行; 小野信任; 増田弘生; 中島英斉; 奥村隆昌; 橋本昌宜; 佐藤高史
第20回回路とシステム軽井沢ワークショップ, Apr. 2007

Improvement of Power Distribution Network Using Correlation-based Regression Analysis
S. Hagiwara; T. Uezono; T. Sato; K. Masu
ACM Great Lakes Symposium on VLSI (GLSVLSI), Mar. 2007

Adaptable Wire-length Distribution With Tunable Occupation Probability
S. Amakawa; T. Uezono; T. Sato; K. Masu
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Mar. 2007

A MOS Transistor-array for Accurate Measurement of Subthreshold Leakage Variation
T. Sato; T. Uezono; S. Hagiwara; K. Okada; S. Amakawa; N. Nakayama; K. Masu
International Symposium on Quality Electronic Design (ISQED), Mar. 2007

電源解析への相関係数利用の検討
萩原汐; 上薗巧; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2007

非理想的な回路分割とセル占有率を考慮した配線長分布モデル
天川修平; 上薗巧; 佐藤高史; 益一哉
電子情報通信学会総合大会, Mar. 2007

A Multi-drop Transmission-line Interconnect in Si LSI
J. Seita; H. Ito; K. Okada; T. Sato; K. Masu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2007

電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現
小笠原泰弘; 榎並孝司; 橋本昌宜; 佐藤高史; 尾上孝雄
信学技報, Jan. 2007

A Left Handed Material on Si CMOS Chip With Wafer Level Package Process
J. Kim; T. Yammouchi; K. Okada; T. Sato; K. Masu
Asia Pacific Microwave Conference (APMC), Dec. 2006

Thermal Driven Module Placement Using Sequence-pair
M. Okada; C. Kodama; T. Sato; K. Fujiyoshi
Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006

MOSFETのリーク電流ばらつき測定のための回路検討
藤久雄己; 岡田健一; 佐藤高史; 中山範明; 益一哉
システムLSIワークショップ, Nov. 2006

A Time-slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop
T. Sato; Y. Matsumoto; K. Hirakimoto; M. Komoda; J. Mano
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006

Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation
Y. Ogasahara; T. Enami; M. Hashimoto; T. Sato; T. Onoye
IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006

高精度デバイスばらつき測定のための電源構造の設計
萩原汐; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

リングオシレータを用いる瞬時電圧降下測定手法の精度改善
上薗巧; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

伝送線路を用いたオンチップ高速伝送回路の研究
清田淳紀; 伊藤浩之; 岡田健一; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

Si CMOSチップにおける右手・左手系伝送線路の検討
金章九; 山内拓弥; 岡田健一; 佐藤高史; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

MOSFETのリーク電流ばらつき測定のための回路検討
藤久雄己; 上園巧; 萩原汐; 岡田健一; 佐藤高史; 中山範明; 益一哉
電子情報通信学会ソサイエティ大会, Sep. 2006

統計的 STA の精度検証手法
小林宏行; 小野信任; 佐藤高史; 岩井二郎; 橋本昌宜
DA シンポジウム, Jul. 2006

統計的 SSTA の精度検証方法
小林宏行; 小野信任; 佐藤高史; 岩井二郎; 橋本昌宜
第19回回路とシステム軽井沢ワークショップ, Apr. 2006

オンチップ熱バラツキを考慮したモジュール配置手法
岡田典英; 児玉親亮; 佐藤高史; 藤吉邦洋
DA シンポジウム, Aug. 2005

ジッタ制約を考慮した IO 同時動作設計ルールの提案
蜂屋孝太郎; 小林宏行; 奥村隆昌; 佐藤高史; 岡宏規
第18回回路とシステム軽井沢ワークショップ, Apr. 2005

Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion
T. Sato; M. Hashimoto; H. Onodera
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005

On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
T. Sato; J. Ichimiya; N. Ono; K. Hachiya; M. Hashimoto
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005

Timing Analysis Considering Temporal Supply Voltage Fluctuation
M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005

An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads
T. Sato; M. Hashimoto; H. Onodera
The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2004

フロアプランにおけるオンチップ熱ばらつきの解析と対策
佐藤高史; 市宮淳次; 小野信任; 蜂屋孝太郎; 橋本昌宜
DA シンポジウム, Jul. 2004

オンチップ・インダクタンスとは? --モデリングと抽出技術--
黒川敦; 佐藤高史; 金本俊幾
DA シンポジウム, Jul. 2003

VLSI 設計・信号品質解析におけるインダクタンスの影響とその重要性
佐藤高史; 金本俊幾; 黒川敦
DA シンポジウム, Jul. 2003

A Statistical Methodology for Screening Inductance Dominated Interconnects in Timing Analysis
T. Kanamoto; T. Sato; A. Kurokawa; Y. Kawakami; H. Oka; T. Kitaura; H. Kobayashi; M. Hashimoto
Information Processing Society of Japan, May 2003

電源・グランド間容量が同時切替えノイズに与える影響の解析
坂田和之; 佐藤高史; 横溝剛一
第17回回路とシステム(軽井沢)ワークショップ, Apr. 2003

Design and Measurement of an Inductance-oscillator for Analyzing Inductance Impact on On-chip Interconnect Delay
T. Sato; H. Masuda
International Symposium on Quality Electronic Design (ISQED), Mar. 2003

Approximate Formulae Approach for Efficient Inductance Extraction
A. Kurokawa; T. Sato; H. Masuda
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2003

Accurate Prediction of the Impact of On-chip Inductance on Interconnect Delay Using Electrical and Physical Parameter-based RSF
T. Sato; T. Kanamoto; A. Kurokawa; Y. Kawakami; H. Oka; T. Kitaura; H. Kobayashi; M. Hashimoto
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2003

インダクタンスに起因する配線遅延変動の統計的予測手法
佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
電子情報通信学会ソサイエティ大会チュートリアル講演, Sep. 2002

0.1-um級 LSI の遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法
金本俊幾; 佐藤高史; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
DA シンポジウム, Jul. 2002

動的電源ノイズ解析のための電源グリッドモデル抽出
蜂屋孝太郎; 黒川敦; 佐藤高史; 南文裕; 増田弘生
DAシンポジウム, Jul. 2002

斜め配線を含む VLSIの高速オンチップ・インダクタンス解析
黒川敦; 蜂屋孝太郎; 佐藤高史; 徳升一也; 増田弘生
第15回回路とシステム(軽井沢)ワークショップ, Apr. 2002

インダクタンスが配線遅延に及ぼす影響の定量的評価方法
佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏之; 橋本昌宜
第15回回路とシステム(軽井沢)ワークショップ, Apr. 2002

有限要素法と回路解析の連成解析による同時切替えノイズの評価
馬淵雄一; 諏訪元大; 中村篤; 福本英士; 白井優之; 林亨; 横溝剛一; 佐藤高史; 大竹成典; 坂田和之
第14回エレクトロニクス実装学会全国大会, Mar. 2002

Efficient Generation of Delay Change Curves for Noise-aware Static Timing Analysis
K. Agarwal; Y. Cao; T. Sato; D. Sylvester; C. Hu
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2002

New Approaches to Noise-aware Static Timing Analysis
Y. Cao; T. Sato; X. Huang; C. Hu; D. Sylvester
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Dec. 2000

Characterization of Interconnect Coupling Noise Using In-situ Delay-change Curve Measurements
T. Sato; Y. Cao; D. Sylvester; C. Hu
13th IEEE International ASIC/SOC Conference, Sep. 2000

クロストークノイズによる配線遅延の変動とノイズ波形のモデル化に関する検討
Takashi Sato; Yu Cao; Dennis Sylvester; Chenming Hu
信学技報, Sep. 2000

プリント回路基板の高周波電流解析用 LSI モデリング手法の検討
大竹成典; 馬淵雄一; 林亨; 佐藤高史; 横溝剛一; 白川真司; 福本英士; 中村篤
信学技報, Jul. 2000

New Paradigm of Predictive CMOS Modeling for Early Circuit Simulation
Y. Cao; T. Sato; M. Orshansky; D. Sylvester; C. Hu
IEEE Custom Integrated Circuits Conference (CICC), May 2000

Accurate In-situ Measurement of Peak Noise and Delay Induced by Interconnect Coupling
T. Sato; D. Sylvester; Y. Cao; C. Hu
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2000

A 5 GBytes/s Data Transfer Scheme With Bit-to-bit Skew Control for Synchronous DRAM
T. Sato; Y. Nishio; T. Sugano; Y. Nakagome
International Symposium on VLSI Circuits, Jun. 1998

ビット間スキュー制御を有するシンクロナス DRAM の 5 GByte/s データ伝送技術
佐藤高史; 西尾洋二; 管野利夫; 中込儀延
信学技報, Jun. 1998

A practical row interchanging algorithm for hierarchically constructed circuit matrices using modified modal analysis
佐藤高史; 見山見可子; 横溝剛一; 仁保宏二郎
信学技報, Dec. 1997

メモリ回路を用いた回路分割型回路シミュレーションの評価
見山美可子; 佐藤高史; 北城三郎; 仁保宏二郎
信学技報, Apr. 1996

機能関数を用いたアナログ/デジタル混在回路機能検証高速化手法の一検討
佐藤高史; 信澤理子; 見山美可子; 横溝剛一
電子情報通信学会総合大会, Mar. 1994

Books and Other Publications

VLSI Design and Test for Systems Dependability
Takashi Sato, Contributor, Chapter 6, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design
Springer, Apr. 2019, Not refereed
Find Kyoto University's collection of books :

Circuit Design for Reliability
Reis, Cao; Wir, Contributor, Chapter 5
Springer, Nov. 2014, Not refereed
Find Kyoto University's collection of books :

Bias Temperature Instability for Devices and Circuits
Grasser, Tibor, Contributor, Chapter 19 and 20, pp.719-782,
Springer, Dec. 2013, Not refereed

動画像からのロバストな心拍数推定
佐藤高史, Contributor
技術情報協会

Industrial Property Rights

特願2020-205323, 情報処理装置、コンピュータプログラム、情報処理方法及びシミュレーション情報提供方法
佐藤高史; 塚本裕貴; 辺松

特願2018-154477, ＰＵＦ回路群，ＰＵＦ回路群の製造方法，ＰＵＦ回路の使用方法，及びネットワークシステム
佐藤高史; 田中悠貴; 辺松; 廣本正之

特願2013-020277, 太陽電池、複合太陽電池および集積回路
越智裕之; 池辺卓; 佐藤高史

特開特開2011-197895, 集積回路電源間容量の計算装置、及び、集積回路電源間容量の計算方法
益一哉; 山長功; 萩原汐; 佐藤高史

特許特許5246785, 回路モデル作成装置、回路モデル作成方法、シミュレーション装置、及び、シミュレーション方法
佐藤高史; 山長功; 益一哉

特許2006-511097, 特願2006-511097, 電子回路
諏訪元大; 宮木美典; 林亨; 佐野亮一; 松井重純; 成瀬峰信; 佐藤高史; 塩田恒星

External funds: Kakenhi

Clonable PUF: Physical Unclonable Function with Limited Replication
Grant-in-Aid for Challenging Research (Exploratory)
Medium-sized Section 60:Information science, computer engineering, and related fields
Kyoto University
Takashi Sato
From 30 Jul. 2020, To 31 Mar. 2023, Project Closed
物理的複製困難関数;特性ばらつき;認証;セキュリティ;PUF;物理的複製困難回路;ＰＵＦ;ハードウェアセキュリティ
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-20K21793/

Multi-functional and ultra-low-cost disposable healthcare sensors using organic-silicon hybrid circuits
Grant-in-Aid for Scientific Research (B)
Basic Section 60040:Computer system-related
Kyoto University
Sato Takashi
From 01 Apr. 2020, To 31 Mar. 2023, Project Closed
有機トランジスタ;センサ回路;スイッチマトリクス;バイアス生成回路;増幅回路;セレクタ回路;ヘルスケアセンサ;センサ;トランジスタアレイ;ハイブリッド回路
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-20H04156/

不正確演算による深層学習向け高効率計算技術
Grant-in-Aid for Scientific Research (B)
Basic Section 60040:Computer system-related
Kyoto University
廣本正之
From 01 Apr. 2018, To 31 Mar. 2021, Declined
近似計算;ニューラルネットワーク;計算機アーキテクチャ;画像認識;深層学習;不正確演算;プロセッサアーキテクチャ
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18H03214/

Development of Time-Varying Chip-ID Based on Transistor Models Considering Transient Degradation
Grant-in-Aid for Scientific Research (B)
Kyoto University
Takashi Sato
From 01 Apr. 2017, To 31 Mar. 2020, Project Closed
チップID;経年劣化;集積回路設計;認証;暗号;個体識別;暗号・認証;個体認識;集積回路;暗号・認証等
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-17H01713/

Unconscious, non-contact, and continuous bital sensing
Grant-in-Aid for Challenging Exploratory Research
Kyoto University
Takashi Sato
From 01 Apr. 2015, To 31 Mar. 2017, Project Closed
心拍数推定;心拍間隔推定;非接触測定;生体情報;信号処理;脈波推定;ノイズ
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15K12700/

Study on Neural Network Processor for Image Recognition
Grant-in-Aid for Young Scientists (B)
Kyoto University
Masayuki HIROMOTO
From 01 Apr. 2014, To 31 Mar. 2017, Project Closed
画像認識;ニューラルネットワーク;ディープラーニング;低消費電力設計;近似計算;メモリスタ;低消費電力技術
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-26730027/

Reliability design for lifetime prediction, failure prevention, and degradation recovery of integrated circuits
Grant-in-Aid for Scientific Research (B)
Kyoto University
Takashi Sato
From 01 Apr. 2014, To 31 Mar. 2017, Project Closed
電子デバイス;デバイス設計・製造プロセス;シミュレーション;デバイスモデル;大規模アレイ回路;経時特性変化;モデル化
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-26280014/

Architecture for Large-scale Long-term Digital Storage System
Grant-in-Aid for Scientific Research (B)
Ritsumeikan University;Kyoto University
Hiroyuki OCHI
From 01 Apr. 2011, To 31 Mar. 2014, Project Closed
非接触通信;非接触電源供給;オンチップ太陽電池;長期信頼性;マスクROM;アドホックネットワーク
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23300015/

Acceleration of Timing Analysis using Monte Carlo Methods
Grant-in-Aid for Scientific Research (B)
Kyoto University
Takashi SATO
From 01 Apr. 2010, To 31 Mar. 2013, Project Closed
集積回路設計技術;CAD;タイミング解析;モンテカルロ法;集積回路設計;電子回路CAD
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22360143/

Signal Integrity of Nano-Scale interconnect and Circuit
Grant-in-Aid for Scientific Research on Priority Areas
Science and Engineering
Tokyo Institute of Technology
Kazuya MASU
From 01 Apr. 2006, To 31 Mar. 2010, Project Closed
ナノ配線;シグナル・インテグリティ;インテグリティ;揺らぎ;ばらつき;シグナルインテグリティ;ばらっき
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18063008/

Development of On-chip Nano-Scale Network Based on Communication Theory
Grant-in-Aid for Scientific Research (A)
Tokyo Institute of Technology
Kazuya MASU
From 01 Apr. 2004, To 31 Mar. 2008, Project Closed
伝送線路;集積回路;微細配線;高速信号伝送;低消費電力;システムオンチップ;ネットワークオンチップ;配線長分布, transmission line;integrated cirtcuit;nano interconnect;high speed signal propagation;low power consumption;system on chip;network on chip;wire length distribution
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-16206034/

Transistor Array Measurements for Physical Unclonable Function with Flexible Printable Transistors
Grant-in-Aid for Scientific Research (C)
Basic Section 60040:Computer system-related
National Institute of Advanced Industrial Science and Technology
小笠原泰弘
From 01 Apr. 2022, To 31 Mar. 2025, Granted
有機トランジスタ;フレキシブルデバイス;測定技術;多素子測定;信頼性評価;フレキシブル;ばらつき;PUF;ハードウェアセキュリティ
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22K11966/

Scalable silicon reservoir computing
Grant-in-Aid for Scientific Research (B)
Basic Section 60040:Computer system-related
Kyoto University
佐藤高史
From 01 Apr. 2023, To 31 Mar. 2026, Granted
シリコンリザバー;クロスバアレイ;リザバー表現;エコーステートネットワーク
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23H03362/

DNA記憶装置による高機能演算の実現
Grant-in-Aid for Challenging Research (Exploratory)
Medium-sized Section 60:Information science, computer engineering, and related fields
Kyoto University
佐藤高史
From 30 Jun. 2023, To 31 Mar. 2026, Granted
デオキシリボ核酸;DNA記憶装置;超並列検索
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23K18462/

Scalable Silicon Reservoir Computing
Grant-in-Aid for Scientific Research (B)
Basic Section 60040:Computer system-related
Kyoto University
佐藤高史
From 01 Apr. 2023, To 31 Mar. 2026, Granted
シリコンリザバー;クロスバアレイ;リザバー表現;エコーステートネットワーク;遅延フィードバック型リザバー
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23K28052/

Last Updated :2025/04/23

Education

Teaching subject(s)

From 01 Apr. 2024, To 31 Mar. 2025
Integraged Circuits Engineering
6113, Spring, Faculty of Engineering, 2

From 01 Apr. 2024, To 31 Mar. 2025
Embedded Computer Systems
6111, Fall, Faculty of Engineering, 2

From 01 Apr. 2024, To 31 Mar. 2025
Computer Hardware Design
6016, Fall, Faculty of Engineering, 2

From 01 Apr. 2024, To 31 Mar. 2025
System-Level Design Methodology for SoCs
3635, Fall, Graduate School of Informatics, 2

From 01 Apr. 2024, To 31 Mar. 2025
Design in ICT
3689, Fall, Graduate School of Informatics, 2

From 01 Apr. 2024, To 31 Mar. 2025
Integrated System Architecture and Synthesis
3677, Spring, Graduate School of Informatics, 2

From 01 Apr. 2023, To 31 Mar. 2024
Integraged Circuits Engineering
6113, Spring, Faculty of Engineering, 2

From 01 Apr. 2023, To 31 Mar. 2024
Embedded Computer Systems
6111, Fall, Faculty of Engineering, 2

From 01 Apr. 2023, To 31 Mar. 2024
Computer Hardware Design
6016, Fall, Faculty of Engineering, 2

From 01 Apr. 2023, To 31 Mar. 2024
System-Level Design Methodology for SoCs
3635, Fall, Graduate School of Informatics, 2

From 01 Apr. 2023, To 31 Mar. 2024
Design in ICT
3689, Fall, Graduate School of Informatics, 2

From 01 Apr. 2023, To 31 Mar. 2024
Integrated System Architecture and Synthesis
3677, Spring, Graduate School of Informatics, 2

From 01 Apr. 2022, To 31 Mar. 2023
Computer Hardware Design
6016, Fall, Faculty of Engineering, 2

From 01 Apr. 2022, To 31 Mar. 2023
System-Level Design Methodology for SoCs
3635, Fall, Graduate School of Informatics, 2

From 01 Apr. 2022, To 31 Mar. 2023
Integraged Circuits Engineering
6113, Spring, Faculty of Engineering, 2

From 01 Apr. 2022, To 31 Mar. 2023
Integrated System Architecture and Synthesis
3677, Spring, Graduate School of Informatics, 2

From 01 Apr. 2022, To 31 Mar. 2023
Design in ICT
3689, Fall, Graduate School of Informatics, 2

From 01 Apr. 2022, To 31 Mar. 2023
Embedded Computer Systems
6111, Fall, Faculty of Engineering, 2

From Apr. 2011, To Mar. 2012
Advanced Study in CCE II
Year-long, 情報学研究科

From Apr. 2011, To Mar. 2012
Advanced Study in CCE I
Year-long, 情報学研究科

From Apr. 2011, To Mar. 2012
通信情報システム特別研究１
Year-long, 情報学研究科

From Apr. 2011, To Mar. 2012
通信情報システム特別研究２
Year-long, 情報学研究科

From Apr. 2011, To Mar. 2012
集積システム設計論
Fall, 情報学研究科

From Apr. 2011, To Mar. 2012
応用集積システム
Spring, 情報学研究科

From Apr. 2011, To Mar. 2012
通信情報システム特別セミナー
Year-long, 情報学研究科

From Apr. 2011, To Mar. 2012
集積システム工学特別セミナー
Year-long, 情報学研究科

From Apr. 2012, To Mar. 2013
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2012, To Mar. 2013
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2012, To Mar. 2013
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2012, To Mar. 2013
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2012, To Mar. 2013
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2012, To Mar. 2013
High-Level Design Methodology for System LSI
Fall, 情報学研究科

From Apr. 2013, To Mar. 2014
Computer Hardware Design
Fall, 工学部

From Apr. 2013, To Mar. 2014
Embedded Computer Systems
Fall, 工学部

From Apr. 2013, To Mar. 2014
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2013, To Mar. 2014
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2013, To Mar. 2014
Advanced Study in Communications and Computer Engineering I
Spring, 情報学研究科

From Apr. 2013, To Mar. 2014
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2013, To Mar. 2014
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2013, To Mar. 2014
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2013, To Mar. 2014
Design in ICT
Spring, 情報学研究科

From Apr. 2013, To Mar. 2014
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2013, To Mar. 2014
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Computer Hardware Design
Fall, 工学部

From Apr. 2014, To Mar. 2015
Embedded Computer Systems
Fall, 工学部

From Apr. 2014, To Mar. 2015
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2014, To Mar. 2015
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2014, To Mar. 2015
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2014, To Mar. 2015
Design in ICT
Spring, 情報学研究科

From Apr. 2014, To Mar. 2015
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2014, To Mar. 2015
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2015, To Mar. 2016
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2015, To Mar. 2016
Design in ICT
Spring, 情報学研究科

From Apr. 2015, To Mar. 2016
Embedded Computer Systems
Fall, 工学部

From Apr. 2015, To Mar. 2016
Computer Hardware Design
Fall, 工学部

From Apr. 2015, To Mar. 2016
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering II
Spring, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering I
Fall, 情報学研究科

From Apr. 2015, To Mar. 2016
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2015, To Mar. 2016
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2015, To Mar. 2016
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2016, To Mar. 2017
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2016, To Mar. 2017
Design in ICT
Spring, 情報学研究科

From Apr. 2016, To Mar. 2017
Embedded Computer Systems
Fall, 工学部

From Apr. 2016, To Mar. 2017
Computer Hardware Design
Fall, 工学部

From Apr. 2016, To Mar. 2017
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering II
Fall, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering I
Spring, 情報学研究科

From Apr. 2016, To Mar. 2017
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2016, To Mar. 2017
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2016, To Mar. 2017
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2017, To Mar. 2018
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2017, To Mar. 2018
Design in ICT
Spring, 情報学研究科

From Apr. 2017, To Mar. 2018
Embedded Computer Systems
Fall, 工学部

From Apr. 2017, To Mar. 2018
Computer Hardware Design
Fall, 工学部

From Apr. 2017, To Mar. 2018
Seminar on Communications and Computer Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering II
Spring, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering II
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering I
Spring, 情報学研究科

From Apr. 2017, To Mar. 2018
Advanced Study in Communications and Computer Engineering I
Year-long, 情報学研究科

From Apr. 2017, To Mar. 2018
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2017, To Mar. 2018
Seminar on Integrated Systems Engineering, Advanced
Year-long, 情報学研究科

From Apr. 2018, To Mar. 2019
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2018, To Mar. 2019
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2018, To Mar. 2019
Design in ICT
Spring, 工学研究科

From Apr. 2018, To Mar. 2019
Design in ICT
Spring, 情報学研究科

From Apr. 2018, To Mar. 2019
Embedded Computer Systems
Fall, 工学部

From Apr. 2018, To Mar. 2019
Computer Hardware Design
Fall, 工学部

From Apr. 2018, To Mar. 2019
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2019, To Mar. 2020
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2019, To Mar. 2020
Design in ICT
Fall, 情報学研究科

From Apr. 2019, To Mar. 2020
Embedded Computer Systems
Fall, 工学部

From Apr. 2019, To Mar. 2020
Computer Hardware Design
Fall, 工学部

From Apr. 2019, To Mar. 2020
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2019, To Mar. 2020
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2020, To Mar. 2021
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2020, To Mar. 2021
Design in ICT
Fall, 情報学研究科

From Apr. 2020, To Mar. 2021
Embedded Computer Systems
Fall, 工学部

From Apr. 2020, To Mar. 2021
Computer Hardware Design
Fall, 工学部

From Apr. 2020, To Mar. 2021
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2020, To Mar. 2021
System-Level Design Methodology for SoCs
Fall, 情報学研究科

From Apr. 2021, To Mar. 2022
Integrated System Architecture and Synthesis
Spring, 情報学研究科

From Apr. 2021, To Mar. 2022
Design in ICT
Fall, 情報学研究科

From Apr. 2021, To Mar. 2022
Embedded Computer Systems
Fall, 工学部

From Apr. 2021, To Mar. 2022
Computer Hardware Design
Fall, 工学部

From Apr. 2021, To Mar. 2022
Integraged Circuits Engineering
Spring, 工学部

From Apr. 2021, To Mar. 2022
System-Level Design Methodology for SoCs
Fall, 情報学研究科

Participation in PhD Defense

In-Band Full-Duplex Transmission for Next Generation Mobile Communication
MORI SHOTA, Graduate School of Informatics, Sub-chief Examiner
25 Mar. 2024

Leakage-Current-Aware Layout Design of DNTT-Based OTFTs and Its Applications to Digital Circuits
OSHIMA KUNIHIRO, Graduate School of Informatics, Chief Examiner
25 Mar. 2024

Fault-Resilient Resource Allocation in Network Function Virtualization
KANG RUI, Graduate School of Informatics, Sub-chief Examiner
25 Sep. 2023

Robust Design of Low-voltage OTFT Circuits for Flexible Electronic Systems
QIN ZHAOXING, Graduate School of Informatics, Chief Examiner
23 Mar. 2023

オンチップ電源電圧変動を考慮したLSI-coreマクロモデルに関する研究
TANAKA HIROSHI, Graduate School of Engineering, Sub-chief Examiner
23 Mar. 2023

電力変換回路におけるパワーモジュールの熱設計に向けた特性測定とモデリング
NAKAMURA YOHEI, Graduate School of Informatics, Chief Examiner
23 Mar. 2023

Design and Verification of Single-Flux-Quantum Digital Circuits Using Clocked and Clockless Gates
KAWAGUCHI TAKAHIRO, Graduate School of Informatics, Sub-chief Examiner
23 Jan. 2023

Last Updated :2025/04/23

Administration

School management (title, position)

From 01 Apr. 2024
大学評価委員会点検・評価実行委員会委員

From 01 Apr. 2010, To 31 Mar. 2011
学生部委員会委員

From 01 Apr. 2010, To 31 Mar. 2012
学生生活委員会委員

From 01 Apr. 2014, To 31 Mar. 2015
教育用計算機専門委員会委員

From 01 Apr. 2015, To 31 Mar. 2017
広報委員会委員

From 01 Apr. 2015, To 31 Mar. 2017
広報委員会紅萠編集専門部会

From 01 Apr. 2015, To 31 Mar. 2017
広報委員会紅萠編集専門部会

Faculty management (title, position)

From 01 Apr. 2023, To 31 Mar. 2025
連携推進WG委員

From 01 Apr. 2023, To 31 Mar. 2025
人を対象とする研究倫理小委員会委員

From 01 Apr. 2023, To 31 Mar. 2025
評価・広報委員会委員長

From 01 Apr. 2023, To 31 Mar. 2025
人権委員会委員

From 01 Apr. 2023, To 31 Mar. 2025
情報学研究科副研究科長

From 01 Apr. 2020, To 31 Mar. 2023
教務委員会委員

From 01 Apr. 2022, To 31 Mar. 2023
人を対象とする研究倫理小委員会委員

From 01 Apr. 2022, To 31 Mar. 2023
専攻長

From 01 Apr. 2022, To 31 Mar. 2023
制規委員会委員

From 01 Apr. 2022, To 31 Mar. 2023
情報セキュリティ委員会　委員

From 01 Apr. 2011, To 31 Mar. 2012
専攻長会議

From 01 Apr. 2011, To 31 Mar. 2012
制規委員会副委員長

From 01 Apr. 2011, To 31 Mar. 2012
情報セキュリティ委員会委員

From 01 Apr. 2012, To 31 Mar. 2014
企画委員会委員

From 01 Apr. 2014, To 31 Mar. 2015
基盤整備委員会委員

From 01 Apr. 2014, To 31 Mar. 2015
計算機小委員会委員長(基盤整備員会)

From 01 Apr. 2015, To 31 Mar. 2016
基盤整備委員会委員長

From 01 Apr. 2016, To 31 Mar. 2017
評価・広報委員会委員

From 01 Apr. 2016, To 31 Mar. 2017
教務委員会委員

From 01 Apr. 2016, To 31 Mar. 2017
第３期中期目標期間部局行動計画作成ＷＧ委員

From 01 Apr. 2016, To 31 Mar. 2017
評価ＷＧ副委員長

From 01 Apr. 2016, To 31 Mar. 2017
広報ＷＧ委員

From 01 Apr. 2017, To 31 Mar. 2018
専攻長会議

From 01 Apr. 2017, To 31 Mar. 2018
情報背急ティ委員会委員

From 01 Jun. 2018, To 31 Mar. 2019
教務委員会委員

From 01 Apr. 2018, To 31 Mar. 2019
財務委員会副委員長

From 01 Apr. 2019, To 31 Mar. 2020
財務委員会委員長

From 01 Apr. 2020, To 31 Mar. 2022
企画委員会委員

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Sato, Takashi

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External funds: Kakenhi

Education

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Participation in PhD Defense

Administration

School management (title, position)

Faculty management (title, position)