Basic Information

Faculty

• 工学部

Academic Degree

• Ph.D. in Informatics(Kyoto University)
• Master degree in Engineering(Kyoto Unviersity)

Academic Resume (Graduate Schools)

• Kyoto University, Graduate School of Engineering, 修了
• Kyoto Univesity, Graduate School of Informatics, Department of Communications and Computer Engineering, 修了

Academic Resume (Undergraduate School/Majors)

• Kyoto University, School of Engineering, 卒業

Profile

• Profile

  1997年 3月25日 京都大学工学部電子学科卒業
  1999年 3月23日 京都大学大学院工学研究科電子通信工学専攻 修士課程修了
  2000年 1月 1日 日本学術振興会特別研究員 (2001年3月31日まで)
  2001年 3月23日 京都大学大学院情報学研究科通信情報システム工学専攻 博士課程修了
  2001年 3月23日 博士号取得（京都大学博士(情報学) 通信情報システム工学専攻）
  2001年 4月 1日 京都大学情報学研究科、助手
  2001年 12月 1日 科学技術振興機構、さきがけ研究 研究員 (兼務, 2005年3月31まで)
  2004年 4月 1日 大阪大学大学院情報科学研究科 助教授
  2004年 4月 1日 京都大学大学院情報学研究科 非常勤講師 (兼務, 2005年3月31まで)
  2007年 4月 1日 大阪大学大学院情報科学研究科 准教授
  2016年 4月 1日 大阪大学大学院情報科学研究科 教授
  2021年 4月 1日 京都大学大学院情報学研究科 教授

ID,URL

• J-Global ID

  200901005693770718

• Researcher number

  80335207

• External link

  https://sites.google.com/view/masanorihashimoto/

Website(s) (URL(s))

• https://sites.google.com/view/masanorihashimoto/
• https://vlsi.cce.i.kyoto-u.ac.jp/

researchmap URL

• https://researchmap.jp/masanorihashimoto

Research

Research Topics, Overview of the research

• Research Topics

  Integrated System Design and Its Design Methodology

• Overview of the research

  Aiming at 'Creating the Infrastructure for Computing', we are exploring innovative solutions such as designing reliable high-performance computers, developing next-generation FPGAs, and conducting research in secure computing. We are also working towards the realization of a new infrastructure that allows humans to unconsciously exchange information with computing. Toward the realization of next-generation computing based on new principles, we are advancing research in energy-efficient computing and approximate computing.

Research Interests

• Integrated Circuit Design
• 集積回路設計

Research Areas

• Informatics, Computer systems

Papers

• Experimental Study of Proton-Induced Radiation Effects on DDR5 Modules

  Yang Li; Masakazu Yoshida; Yuibi Gomi; Yifan Deng; Yukinobu Watanabe; Satoshi Adachi; Masatoshi Itoh; Guohe Zhang; Chaohui He; Masanori Hashimoto

  IEEE Transactions on Nuclear Science, 2025

  
• A Current Chopper-assisted Magnetic Field-based Backscatter Communication Method with WPT Overcoming Ultra-low Coupling Coefficients

  Ryota Fukugasako; Hisafumi Asaue; Tomoki Shiotani; Masanori Hashimoto; Ryo Shirai

  IEEE Sensors Journal, 2025

  
• Development of Tiny Wireless Position Tracker Enabling Real-Time Intuitive 3D Modeling

  Yuki Maegawa; Masanori Hashimoto; Ryo Shirai

  SIGGRAPH Asia 2024 Posters, 02 Dec. 2024

  
• Validating Terrestrial SER in 12-, 28- and 65-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation

  Kazusa Takami; Yuibi Gomi; Ryuichi Yasuda; Shin-ichiro Abe; Masatoshi Itoh; Hiroki Kanda; Mitsuhiro Fukuda; Masanori Hashimoto

  IEEE Transactions on Nuclear Science, 2025

  
• A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture

  Toshihiro Kameda; Hiroaki Konoura; Dawood Alnajjar; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, 2012, Peer-reviewed

  
• Analytical Equivalent Circuit Extraction of Foreign Metal Objects in WPT Systems

  Ryo Shirai; Goro Nakao; Masanori Hashimoto

  IEEE Access, 2024

  
• Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory

  Alioto, M.; Abadir, M.S.; Arslan, T.; Boon, C.C.; Burg, A.; Chang, C.-H.; Chang, M.-F.; Chang, Y.-W.; Chen, P.; Corsonello, P.; Crovetti, P.; Dosho, S.; Drechsler, R.; Elfadel, I.A.M.; Han, R.; Hashimoto, M.; Heng, C.-H.; Heo, D.; Ho, T.-Y.; Homayoun, H.; Hwang, Y.-S.; Joshi, A.; Joshi, R.V.; Karnik, T.; Kim, C.; Kim; T.-H.T.; Kulkarni, J.; Kursun, V.; Lee, Y.; Li, H.H.; Li, H.; Mishra, P.; Mohammad, B.; Kermani, M.M.; Nagata, M.; Nii, K.; Pande, P.P.; Paul, B.C.; Pavlidis, V.F.; De Gyvez, J.P.; Savidis, I.; Schaumont, P.; Sebastiano, F.; Sengupta, A.; Seok, M.; Stan, M.R.; Tehranipoor, M.M.; Todri-Sanial, A.; Verhelst, M.; Vignoli, V.; Wen, X.; Xu, J.; Zhang, W.; Zhang, Z.; Zhou, J.; Zwolinski, M.; Weber, S.

  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019

  
• Modeling the effect of global layout pattern on wirewidth variation for on-the-fly etching process modification

  Fukuda, D.; Watanabe, K.; Kanazawa, Y.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2015

  
• Foreword: Special section on VLSI design and CAD algorithms

  Yamada, A.; Higami, Y.; Takagi, K.; Amagasaki, M.; Ikeda, M.; Ishihara, T.; Ito, K.; Usami, K.; Okada, K.; Kajihara, S.; Kaneko, M.; Kawaguchi, H.; Kimura, S.; Kurokawa, A.; Shibata, Y.; Seto, K.; Song, T.; Takashima, Y.; Takahashi, A.; Takenaka, T.; Togawa, N.; Tomiyama, H.; Nakatake, S.; Nakamura, Y.; Hashimoto, M.; Hamaguchi, K.; Higuchi, H.; Hirose, T.; Fukuda, D.; Matsumoto, T.; Miura, Y.; Minato, S.-I.; Minami, F.; Yamashita, S.; Yuminaka, Y.; Yoshikawa, M.; Watanabe, T.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014

  
• Exploring well-configurations for minimizing single event latchup

  Uemura, T.; Kato, T.; Tanabe, R.; Iwata, H.; Ariyoshi, J.; Matsuyama, H.; Hashimoto, M.

  IEEE Transactions on Nuclear Science, 2014

  
• Edge-over-erosion error prediction method based on multi-level machine learning algorithm

  Fukuda, D.; Watanabe, K.; Idani, N.; Kanazawa, Y.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014

  
• Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width measurement

  Harada, R.; Mitsuyama, Y.; Hashimoto, M.; Onoye, T.

  IEEE Transactions on Nuclear Science, 2013

  
• Statistical timing analysis considering clock jitter and skew due to power supply noise and process variation

  Enami, T.; Ninomiya, S.; Shinkai, K.-I.; Abe, S.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010

  
• Gate delay estimation in STA under dynamic power supply noise

  Okumura, T.; Minami, F.; Shimazaki, K.; Kuwada, K.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010

  
• Accuracy enhancement of grid-based SSTA by coefficient interpolation

  Ninomiya, S.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010

  
• Transistor sizing of LCD driver circuit for technology migration

  Hashimoto, M.; Ijichi, T.; Takahashi, S.; Tsukiyama, S.; Shirakawa, I.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2007

  
• A sampling switch design procedure for active matrix liquid crystal displays

  Takahashi, S.; Tsukiyama, S.; Hashimoto, M.; Shirakawa, I.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2006

  
• Special section on recent advances in circuits and systems - Part 1

  Akutsu, T.; Amagasa, T.; Arakawa, K.; Asano, A.; Fujita, S.; Fukumi, M.; Ge, Q.-W.; Hashimoto, M.; Ichige, K.; Isshiki, T.; Itoh, Y.; Kajikawa, Y.; Kaneda, K.; Kinjo, S.; Kiya, H.; Kohata, M.; Kondo, K.; Miyanaga, Y.; Murata, H.; Nakajo, H.; Nakanishi, I.; Nakashizuka, M.; Nakayama, K.; Nishikawa, K.; Nishimura, S.; Nishio, Y.; Ochi, H.; Ohno, S.; Saeki, M.; Taguchi, A.; Takafuji, D.; Takahashi, A.; Taoka, S.; Tsuji, T.; Ushio, T.; Xiao, Y.; Yamamoto, O.; Yamamoto, T.; Yoshinaga, T.; Hinamoto, T.; Watanabe, T.

  IEICE Transactions on Information and Systems, 2005

  
• Special section on recent advances in Circuits and Systems - Part 2

  Akutsu, T.; Amagasa, T.; Arakawa, K.; Asano, A.; Fujita, S.; Fukumi, M.; Ge, Q.-W.; Hashimoto, M.; Ichige, K.; Isshiki, T.; Itoh, Y.; Kajikawa, Y.; Kaneda, K.; Kinjo, S.; Kiya, H.; Kohata, M.; Kondo, K.; Miyanaga, Y.; Murata, H.; Nakajo, H.; Nakanishi, I.; Nakashizuka, M.; Nakayama, K.; Nishikawa, K.; Nishimura, S.; Nishio, Y.; Ochi, H.; Ohno, S.; Saeki, M.; Taguchi, A.; Takafuji, D.; Takahashi, A.; Taoka, S.; Tsuji, T.; Ushio, T.; Xiao, Y.; Yamamoto, O.; Yamamoto, T.; Yoshinaga, T.; Hinamoto, T.; Watanabe, T.

  IEICE Transactions on Information and Systems, 2005

  
• SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects

  Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEEE International Reliability Physics Symposium Proceedings, 2012

  
• Implications of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures

  Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011, 2011

  
• Adaptive performance compensation with on-chip variation monitoring

  Masanori Hashimoto; Hiroshi Fuketa

  Midwest Symposium on Circuits and Systems, 2011

  
• NBTI mitigation by giving random scan-in vectors during standby mode

  Toshihiro Kameda; Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2011

  
• Feasibility evaluation on an instant invader detection system with ultrasonic sensors scattered on the ground

  Ami Iokibe; Masanori Hashimoto; Takao Onoye

  International Journal on Smart Sensing and Intelligent Systems, 01 Dec. 2014

  
• Hardware Architecture for Fast General Object Detection using Aggregated Channel Features

  Koichi Mitsunari; Jaehoon Yu; Masanori Hashimoto

  2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, 14 Dec. 2018

  
• Feasibility evaluation on an instant invader detection system with ultrasonic sensors scattered on the ground

  Ami Iokibe; Masanori Hashimoto; Takao Onoye

  Proceedings of the International Conference on Sensing Technology, ICST, 2014

  
• Stochastic error rate estimation for adaptive speed control with field delay testing

  Shoichi Iizuka; Masafumi Mizuno; Dan Kuroda; Masanori Hashimoto; Takao Onoye

  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2013

  
• Impact of Irradiation Side on Muon-Induced Single-Event Upsets in 65-nm Bulk SRAMs

  Yifan Deng; Yukinobu Watanabe; Seiya Manabe; Wang Liao; Masanori Hashimoto; Shin-Ichiro Abe; Motonobu Tampo; Yasuhiro Miyake

  IEEE Transactions on Nuclear Science, Apr. 2024

  
• Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks

  Quan Cheng; Mingqiang Huang; Changhai Man; Ao Shen; Liuyao Dai; Hao Yu; Masanori Hashimoto

  IEEE Transactions on Circuits and Systems I: Regular Papers, Oct. 2023, Peer-reviewed

  
• Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication

  Riku Iwamoto; Masanori Hashimoto

  2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 03 Jul. 2023, Peer-reviewed

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• Bridging the Gap Between Reservoirs and Neural Networks

  Masanori Hashimoto; Ángel López García-Arias; Jaehoon Yu

  Photonic Neural Networks with Spatiotemporal Dynamics, 17 Oct. 2023

  
• Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs

  Wang Liao; Masanori Hashimoto; Seiya Manabe; Yukinobu Watanabe; Shin Ichiro Abe; Keita Nakano; Hayato Takeshita; Motonobu Tampo; Soshi Takeshita; Yasuhiro Miyake

  IEEE International Reliability Physics Symposium Proceedings, 22 May 2019

  
• A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier

  Quan Cheng; Liuyao Dai; Mingqiang Huang; Ao Shen; Wei Mao; Masanori Hashimoto; Hao Yu

  IEEE Transactions on Circuits and Systems II: Express Briefs, Jun. 2023, Peer-reviewed

  
• A Terrestrial SER Estimation Methodology Based on Simulation Coupled With One-Time Neutron Irradiation Testing

  Shin-Ichiro Abe; Masanori Hashimoto; Wang Liao; Takashi Kato; Hiroaki Asai; Kenichi Shimbo; Hideya Matsuyama; Tatsuhiko Sato; Kazutoshi Kobayashi; Yukinobu Watanabe

  IEEE Transactions on Nuclear Science, Aug. 2023, Peer-reviewed

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• Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers

  Minoru Harimaya; Ryo Shirai; Masanori Hashimoto

  28th International Conference on Intelligent User Interfaces, 27 Mar. 2023

  
• Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons

  Kazusa Takami; Yuibi Gomi; Shin-Ichiro Abe; Wang Liao; Seiya Manabe; Tetsuro Matsumoto; Masanori Hashimoto

  2023 IEEE International Reliability Physics Symposium (IRPS), Mar. 2023, Peer-reviewed

  
• Study of Muon Capture Reaction on Si Via In-Beam Muon Activation

  R. Mizuno; M. Niikura; T; Y. Saito; S. Abe; H. Fukuda; M. Hashimoto; K. Ishida; N. Kawamura; S. Kawase; T. Matsuzaki; M. Oishi; P. Strasser; A. Sato; K. Shimomura; S. Takeshita; I. Umegaki

  Topical Workshops on Modern Aspects of Nuclear Structure, Feb. 2023

  
• Recurrent Residual Networks Contain Stronger Lottery Tickets

  Ángel López García-Arias; Yasuyuki Okoshi; Masanori Hashimoto; Masato Motomura; Jaehoon Yu

  IEEE Access, 2023

  
• Processor SER Estimation with ACE Bit Analysis

  Ting-Shuo Hsu; Dun-an Yang; Wang Liao; Masatoshi Itoh; Masanori Hashimoto; Jing-Jia Liou

  2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2021

  
• BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA.

  Hiromitsu Awano; Masanori Hashimoto

  2020 Design(DATE), 2020

  
• Measurement and mechanism investigation of negative and positive muon-induced upsets in 65-nm Bulk SRAMs

  Wang Liao; Masanori Hashimoto; Seiya Manabe; Yukinobu Watanabe; Shin Ichiro Abe; Keita Nakano; Hikaru Sato; Tadahiro Kin; Koji Hamada; Motonobu Tampo; Yasuhiro Miyake

  IEEE Transactions on Nuclear Science, Aug. 2018

  
• Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs

  Wang Liao; Masanori Hashimoto; Seiya Manabe; Yukinobu Watanabe; Shin-Ichiro Abe; Keita Nakano; Hikaru Sato; Tadahiro Kin; Koji Hamada; Motonobu Tampo; Yasuhiro Miyake

  IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Aug. 2018

  
• A Multicore Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions

  Jun Chen; Hajime Kando; Toshiki Kanamoto; Cheng Zhuo; Masanori Hashimoto

  IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, Sep. 2019

  
• An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency Between Supply Voltage, Current Profile and Clock Latency

  Jun Chen; Toshiki Kanamoto; Hajime Kando; Masanori Hashimoto

  2018 IEEE 22ND WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI), 2018

  
• Similarity analysis on neutron- A nd negative muon-induced MCUs in 65-nm bulk SRAM

  Wang Liao; Masanori Hashimoto; Seiya Manabe; Shin Ichiro Abe; Yukinobu Watanabe

  IEEE Transactions on Nuclear Science, Jul. 2019

  
• Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, Peer-reviewed

  
• Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  Proceedings of the International Symposium on Low Power Electronics and Design, 2008, Peer-reviewed

  
• Implementing flexible reliability in a coarse-grained reconfigurable architecture

  Dawood Alnajjar; Hiroaki Konoura; Younghun Ko; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, Peer-reviewed

  
• Impact of well edge proximity effect on timing

  Toshiki Kanamoto; Yasuhiro Ogasahara; Keiko Natsume; Kenji Yamaguchi; Hiroyuki Amishiro; Tetsuya Watanabe; Masanori Hashimoto

  ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, Peer-reviewed

  
• 3D Node Localization from Node-to-Node Distance Information using Cross-Entropy Method

  Shohei Ukawa; Tatsuya Shinada; Masanori Hashimoto; Yuichi Itoh; Takao Onoye

  2015 IEEE VIRTUAL REALITY CONFERENCE (VR), 2015, Peer-reviewed

  
• Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

  Hiroshi Fuketa; Ryo Harada; Masanori Hashimoto; Takao Onoye

  IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, Mar. 2014, Peer-reviewed

  
• Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design

  Hiroaki Konoura; Dawood Alnajjar; Yukio Mitsuyama; Hiroyuki Ochi; Takashi Imagawa; Shinichi Noda; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye

  Proc. of 2013 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2013), 09 Dec. 2013, Peer-reviewed

  
• A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations

  Ken-Ichi Shinkai; Masanori Hashimoto; Takao Onoye

  Integration, the VLSI Journal, Sep. 2013, Peer-reviewed

  
• Real-time supply voltage sensor for detecting/Debugging electrical timing failures

  Miho Ueno; Masanori Hashimoto; Takao Onoye

  Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013, 2013, Peer-reviewed

  
• A process and temperature tolerant oscillator-based true random number generator with dynamic 0/1 bias correction

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, 2013, Peer-reviewed

  
• Feasibility Evaluation of Near-Field Communication in Clay with 1-mm(3) Antenna

  Jin Kono; Masanori Hashimoto; Takao Onoye

  2013 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC 2013), 2013, Peer-reviewed

  
• Clock skew reduction by self-compensating manufacturing variability with on-chip sensors

  Shinya Abe; Ken-Ichi Shinkai; Masanori Hashimoto; Takao Onoye

  Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2010, Peer-reviewed

  
• Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO

  Yasumichi Takai; Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings, 2010, Peer-reviewed

  
• Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution

  Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 2010, Peer-reviewed

  
• Soft Error Resilient VLSI Architecture for Signal Processing

  Dawood Alnajjar; Younghun Ko; Takashi Imagawa; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye

  Proc. of 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2009), 07 Dec. 2009, Peer-reviewed

  
• COARSE-GRAINED DYNAMICALLY RECONFIGURABLE ARCHITECTURE WITH FLEXIBLE RELIABILITY

  Dawood Alnajjar; Younghun Ko; Takashi Imagawa; Hiroaki Konoura; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye

  FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, Peer-reviewed

  
• Future prediction of self-heating in short intra-block wires

  Kenichi Shinkai; Masanori Hashimoto; Takao Onoye

  ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2007, Peer-reviewed

  
• B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA

  Hiromitsu Awano; Masanori Hashimoto

  Integration, Mar. 2023, Peer-reviewed

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• Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation

  Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; Yukio Mitsuyama; Tadahiko Sugibayashi

  Japanese Journal of Applied Physics, 01 Oct. 2022, Peer-reviewed, Invited

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• Fault Mode Analysis of Neural Network-based Object Detection on GPUs with Neutron Irradiation Test

  Yangchao Zhang; Kojiro Ito; Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Masanori Hashimoto

  2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Oct. 2020, Peer-reviewed

  
• DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object

  Toshihisa Tanaka; Ryo Shirai; Masanori Hashimoto

  2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), 07 Aug. 2022, Peer-reviewed

  
• Investigating Small Device Implementation of FRET-based Optical Reservoir Computing

  Masafumi Tanakal; Jaehoon Yu; Masaki Nakagawa; Naoya Tate; Masanori Hashimoto

  2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), 07 Aug. 2022, Peer-reviewed

  
• A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter

  Dehua LIANG; Jun SHIOMI; Noriyuki MIURA; Masanori HASHIMOTO; Hiromitsu AWANO

  IEICE Transactions on Information and Systems, 01 Jul. 2022, Peer-reviewed

  
• Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs

  Ryo Shirai; Masanori Hashimoto

  27th International Conference on Intelligent User Interfaces, 22 Mar. 2022, Peer-reviewed

  
• Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections

  Yangchao Zhang; Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Masanori Hashimoto

  2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 14 Mar. 2022, Peer-reviewed

  
• Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling

  Yutaka MASUDA; Jun NAGAYAMA; TaiYu CHENG; Tohru ISHIHARA; Yoichi MOMIYAMA; Masanori HASHIMOTO

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Mar. 2022, Peer-reviewed

  
• Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization

  TaiYu CHENG; Yutaka MASUDA; Jun NAGAYAMA; Yoichi MOMIYAMA; Jun CHEN; Masanori HASHIMOTO

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Mar. 2022, Peer-reviewed

  
• Vulnerability Estimation of DNN Model Parameters with Few Fault Injections

  Yangchao ZHANG; Hiroaki ITSUJI; Takumi UEZONO; Tadanobu TOBA; Masanori HASHIMOTO

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Mar. 2023, Peer-reviewed

  
• VirtualSync+: Timing Optimization With Virtual Synchronization

  Grace Li Zhang; Bing Li; Xing Huang; Xunzhao Yin; Cheng Zhuo; Masanori Hashimoto; Ulf Schlichtmann

  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2022, Peer-reviewed

  
• Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks

  A. Lopez; M. Hashimoto; M; Motomura,J. Yu

  Proceedings of British Machine Vision Conference (BMVC), Nov. 2021, Peer-reviewed

  
• Mitigating Multi-Bit-Upset With Well-Slits in 28 nm Multi-Bit-Latch

  Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto

  IEEE Transactions on Nuclear Science, Dec. 2013

  
• Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

  Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto

  IEEE Transactions on Nuclear Science, Dec. 2013

  
• Prediction of Self-Heating in Short Intra-Block Wires

  SHINKAI Ken-ichi; HASHIMOTO Masanori; ONOYE Takao

  IEICE Trans. Fundamentals, 01 Mar. 2010

  
• Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration

  HASHIMOTO Masanori; SIRIPORN Jangsombatsiri; TSUCHIYA Akira; ZHU Haikun; CHENG Chung-Kuan

  IEICE Trans. Fundamentals, 01 Dec. 2008

  
• Impact of Well Edge Proximity Effect on Timing

  KANAMOTO Toshiki; OGASAHARA Yasuhiro; NATSUME Keiko; YAMAGUCHI Kenji; AMISHIRO Hiroyuki; WATANABE Tetsuya; HASHIMOTO Masanori

  IEICE Trans. Fundamentals, 01 Dec. 2008

  
• Submarine LED: Wirelessly powered underwater display controlling its buoyancy

  Ryo Shirai; Masanori Hashimoto

  SIGGRAPH Asia 2021 Posters, 14 Dec. 2021, Peer-reviewed

  
• Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: From Bit Upset to SEFI and Erroneous Behavior

  Tomonari Tanaka; Wang Liao; Masanori Hashimoto; Yukio Mitsuyama

  IEEE Transactions on Nuclear Science, Jan. 2022

  
• Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble.

  Koichi Mitsunari; Jaehoon Yu; Takao Onoye; Masanori Hashimoto

  IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

  
• An oscillator-based true random number generator with process and temperature tolerance.

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  The 20th Asia and South Pacific Design Automation Conference(ASP-DAC), 2015

  
• PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

  Alnajjar Dawood; Mitsuyama Yukio; Hashimoto Masanori; Onoye Takao

  IEICE Electron. Express, 2013

  
• Analyzing DUE Errors on GPUs With Neutron Irradiation Test and Fault Injection to Control Flow

  Kojiro Ito; Yangchao Zhang; Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Masanori Hashimoto

  IEEE Transactions on Nuclear Science, Aug. 2021, Peer-reviewed

  
• Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization With Neutrons and Alpha Particles

  Takashi Kato; Motonobu Tampo; Soshi Takeshita; Hiroki Tanaka; Hideya Matsuyama; Masanori Hashimoto; Yasuhiro Miyake

  IEEE Transactions on Nuclear Science, Jul. 2021, Peer-reviewed

  
• Characterizing Energetic Dependence of Low-Energy Neutron-Induced SEU and MCU and Its Influence on Estimation of Terrestrial ser in 65-nm Bulk SRAM

  Liao, W.; Ito, K.; Abe, S.-I.; Mitsuyama, Y.; Hashimoto, M.

  IEEE Transactions on Nuclear Science, Jun. 2021, Peer-reviewed

  
• Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling

  TaiYu Cheng; Masanori Hashimoto

  2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021, Peer-reviewed

  
• Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution

  Masanori Hashimoto; Jun Chen

  2021 China Semiconductor Technology International Conference (CSTIC), 14 Mar. 2021, Peer-reviewed, Invited

  
• MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA

  Takashi Imagawa; Jaehoon Yu; Masanori Hashimoto; Hiroyuki Ochi

  2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 01 Feb. 2021, Peer-reviewed

  
• BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter

  Dehua Liang; Masanori Hashimoto; Hiromitsu Awano

  2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 01 Feb. 2021, Peer-reviewed

  
• Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design

  Yutaka Masuda; Jun Nagayama; TaiYu Cheng; Tohru Ishihara; Yoichi Momiyama; Masanori Hashimoto

  2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 01 Feb. 2021, Peer-reviewed

  
• Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers

  Ryo Shirai; Yuichi Itoh; Masanori Hashimoto

  IEEE Access, Feb. 2021, Peer-reviewed

  
• Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization

  TaiYu Cheng; Yukata Masuda; Jun Nagayama; Yoichi Momiyama; Jun Chen; Masanori Hashimoto

  Proceedings of the 26th Asia and South Pacific Design Automation Conference, 18 Jan. 2021, Peer-reviewed

  
• Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation

  Bai, X.; Banno, N.; Miyamura, M.; Nebashi, R.; Okamoto, K.; Numata, H.; Iguchi, N.; Hashimoto, M.; Sugibayashi, T.; Sakamoto, T.; Tada, M.

  IEEE Journal of Solid-State Circuits, 2021, Peer-reviewed

  
• A fault detection and diagnosis method for via-switch crossbar in non-volatile FPGA

  DOI, R.; BAI, X.; SAKAMOTO, T.; HASHIMOTO, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 01 Dec. 2020, Peer-reviewed

  
• Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles

  T. Kato; M. Tampo; S. Takeshita; Y. Miyake; H; Tanaka; M. Hashimoto

  IEEE Nuclear and Space Radiation Effects Conference (NSREC), Dec. 2020, Peer-reviewed

  
• A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges

  Jun Chen; Masanori Hashimoto

  IEEE Transactions on Components, Packaging and Manufacturing Technology, Nov. 2020, Peer-reviewed

  
• Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing

  Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Kojiro Ito; Masanori Hashimoto

  2020 IEEE International Test Conference (ITC), 01 Nov. 2020, Peer-reviewed

  
• Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction

  J. Chen; M. Hashimoto

  Proceedings of International Test Conference (ITC), Nov. 2020, Peer-reviewed

  
• Low-Cost Reservoir Computing Using Cellular Automata and Random Forests

  A. Lopez; J. Yu; M. Hashimoto

  Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020, Peer-reviewed

  
• Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA

  Ryutaro Doi; Jaehoon Yu; Masanori Hashimoto

  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Oct. 2020, Peer-reviewed

  
• Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training

  Cheng, T.; Masuda, Y.; Chen, J.; Yu, J.; Hashimoto, M.

  Integration, Sep. 2020, Peer-reviewed

  
• Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis

  Ryohei Shimizu; Ryo Shirai; Masanori Hashimoto

  2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2020, Peer-reviewed

  
• Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling

  Y. Masuda; J; Nagayama; T. Cheng; T. Ishihara; Y. Momiyama; M. Hashimoto

  International Workshop on Logic and Synthesis (IWLS), Jul. 2020, Peer-reviewed

  
• Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs

  Takashi Kato; Masanori Hashimoto; Hideya Matsuyama

  IEEE Transactions on Nuclear Science, Jul. 2020, Peer-reviewed

  
• Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs

  Wang Liao; Masanori Hashimoto; Seiya Manabe; Yukinobu Watanabe; Shin-ichiro Abe; Motonobu Tampo; Soshi Takeshita; Yasuhiro Miyake

  IEEE Transactions on Nuclear Science, Jul. 2020, Peer-reviewed

  
• Irradiation Test of 65-nm Bulk SRAMs With DC Muon Beam at RCNP-MuSIC Facility

  Takumi Mahara; Seiya Manabe; Yukinobu Watanabe; Wang Liao; Masanori Hashimoto; Takeshi Y. Saito; Megumi Niikura; Kazuhiko Ninomiya; Dai Tomono; Akira Sato

  IEEE Transactions on Nuclear Science, Jul. 2020, Peer-reviewed

  
• 1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy

  X. Bai; N. Banno; M. Miyamura; R. Nebashi; K. Okamoto; H. Numata; N. Iguchi; M; Hashimoto,T; Sugibayashi; T. Sakamoto; M. Tada

  Technical Digest of VLSI Symposium on Technology, Jun. 2020, Peer-reviewed

  
• Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs

  Wang Liao; Kojiro Ito; Yukio Mitsuyama; Masanori Hashimoto

  2020 IEEE International Reliability Physics Symposium (IRPS), Apr. 2020, Peer-reviewed

  
• Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets

  Shin-ichiro Abe; Tatsuhiko Sato; Junya Kuroda; Seiya Manabe; Yukinobu Watanabe; Wang Liao; Kojiro Ito; Masanori Hashimoto; Masahide Harada; Kenichi Oikawa; Yasuhiro Miyake

  2020 IEEE International Reliability Physics Symposium (IRPS), Apr. 2020, Peer-reviewed

  
• DC Magnetic Field Based 3D Localization With Single Anchor Coil

  Ryo Shirai; Masanori Hashimoto

  IEEE Sensors Journal, 01 Apr. 2020, Peer-reviewed

  
• Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network

  K. Onishi; J. Yu; M. Hashimoto

  Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS), Mar. 2020, Peer-reviewed

  
• Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA

  R. Doi; X. Bai; T. Sakamoto; M. Hashimoto

  Proceedings of Design, Automation and Test in Europe Conference (DATE), Mar. 2020, Peer-reviewed

  
• BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA

  H. Awano; M. Hashimoto

  Proceedings of Design, Automation and Test in Europe Conference (DATE), Mar. 2020, Peer-reviewed

  
• 33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

  Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hirovuki Ochi; Kazutoshi Wakabayashi; Yukio Mitsuyama; Tadahiko Suuibayashi

  2020 IEEE International Solid- State Circuits Conference - (ISSCC), Feb. 2020

  
• Measurement of Single-Event Upsets in 65-nm SRAMs Under Irradiation of Spallation Neutrons at J-PARC MLF

  Junya Kuroda; Yasuhiro Miyake; Seiya Manabe; Yukinobu Watanabe; Kojiro Ito; Wang Liao; Masanori Hashimoto; Shin-ichiro Abe; Masahide Harada; Kenichi Oikawa

  IEEE Transactions on Nuclear Science, 2020, Peer-reviewed

  
• Soft Error and Its Countermeasures in Terrestrial Environment

  Masanori Hashimoto; Wang Liao

  2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2020, Peer-reviewed, Invited

  
• When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies

  Zheyu Yan; Yiyu Shi; Wang Liao; Masanori Hashimoto; Xichuan Zhou; Cheng Zhuo

  2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2020, Peer-reviewed

  
• Distilling Knowledge for Non-Neural Networks

  S. Fukui; J. Yu; M. Hashimoto

  Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), Nov. 2019, Peer-reviewed

  
• Training Data Reduction Using Support Vectors for Neural Networks

  T. Tanio; J. Yu; M. Hashimoto

  Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), Nov. 2019, Peer-reviewed

  
• Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation

  M. Hashimoto; K. Kobayashi; J. Furuta; S. Abe; Y. Watanabe

  Integration, the VLSI Journal, Nov. 2019, Peer-reviewed, Invited

  
• A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform

  S. Sombatsiri; J. Yu; M. Hashimoto; Y. Takeuchi

  Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Oct. 2019, Peer-reviewed

  
• Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF

  J. Kuroda; S. Manabe; Y; Watanabe; K. Ito; W. Liao; M. Hashimoto; S. Abe; M. Harada; K. Oikawa; Y. Miyake

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2019, Peer-reviewed

  
• Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM

  W. Liao; M. Hashimoto; S. Manabe; Y; Watanabe; S. Abe; M. Tampo; S. Takeshita; Y. Miyake

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2019, Peer-reviewed

  
• Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU

  K. Ito; W. Liao; M; Hashimoto; J. Kuroda; S. Manabe; Y; Watanabe; S. Abe; M. Harada; K. Oikawa; Y. Miyake

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2019, Peer-reviewed

  
• Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility

  T. Mahara; S. Manabe; Y; Watanabe; W. Liao; M; Hashimoto,T; Y. Saito; M. Niikura; K. Ninomiya; D. Tomono; A. Sato

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2019, Peer-reviewed

  
• A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions

  J. Chen; H. Kando; T; Kanamoto,C. Zhuo; M. Hashimoto

  IEEE Transactions on Components, Packaging and Manufacturing Technology, Sep. 2019, Peer-reviewed

  
• Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

  Naoki Banno; Koichiro Okamoto; Noriyuki Iguchi; Hiroyuki Ochi; Hidetoshi Onodera; Masanori Hashimoto; Tadahiko Sugibayashi; Toshitsugu Sakamoto; Munehiro Tada

  IEEE Transactions on Electron Devices, Aug. 2019, Peer-reviewed

  
• Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier

  T.-Y. Cheng; J. Yu; M. Hashimoto

  Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Jul. 2019, Peer-reviewed

  
• Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs

  Seiya Manabe; Yukinobu Watanabe; Wang Liao; Masanori Hashimoto; Shin-Ichiro Abe

  IEEE Transactions on Nuclear Science, Jul. 2019, Peer-reviewed

  
• Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM

  W. Liao; M. Hashimoto; S. Manabe; S. Abe; Y. Watanabe

  IEEE Transactions on Nuclear Science, Jul. 2019, Peer-reviewed

  
• MTTF-aware design methodology of adaptively voltage scaled circuit with timing error predictive flip-flop

  Masuda, Y.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2019, Peer-reviewed

  
• Impact of Irradiation Side on Neutron-Induced Single-Event Upsets in 65-nm Bulk SRAMs

  Shinichiro Abe; Wang Liao; Seiya Manabe; Tatsuhiko Sato; Masanori Hashimoto; Yukinobu Watanabe

  IEEE Transactions on Nuclear Science, Jul. 2019, Peer-reviewed

  
• Stochastic analysis on hold timing violation in ultra-low temperature circuits for functional test at room temperature

  Nakayama, T.; Hashimoto, M.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Jul. 2019, Peer-reviewed

  
• Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA

  H. Numata; N. Banno; K. Okamoto; N. Iguchi; H. Hada; M. Hashimoto; T. Sugibayashi; T. Sakamoto; M. Tada

  2019 Silicon Nanoelectronics Workshop (SNW), Jun. 2019, Peer-reviewed

  
• A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints

  J. Chen; M. Hashimoto

  Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), Jun. 2019, Peer-reviewed

  
• Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP

  J. Nagayama; Y. Masuda; M. Takeshige; Y. Ogawa; M. Hashimoto; Y. Momiyama

  Jun. 2019, Peer-reviewed

  
• Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs

  W. Liao; M. Hashimoto; S. Manabe; Y; Watanabe; S. Abe; M. Tampo; S. Takeshita; Y. Miyake

  Proceedings of International Reliability Physics Symposium (IRPS), Apr. 2019, Peer-reviewed

  
• Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate

  Wang LIAO; Masanori HASHIMOTO

  IEICE Transactions on Electronics, 01 Apr. 2019, Peer-reviewed

  
• Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes

  Pei Hao Chen; Ryo Shirai; Masanori Hashimoto

  Proceedings of the 24th International Conference on Intelligent User Interfaces: Companion, 16 Mar. 2019, Peer-reviewed

  
• FPGA を用いた動的電源ノイズ下でのエラー予告FF の動作検証

  西孝将; 増田豊; 橋本昌宜

  電子情報通信学会総合大会, Mar. 2019

  
• Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars

  Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Jaehoon Yu; Masanori Hashimoto

  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 2018, Peer-reviewed

  
• Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture

  Hiroki Hihara; Akira Iwasaki; Masanori Hashimoto; Hiroyuki Ochi; Yukio Mitsuyama; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Tadahiko Sugibayashi; Takashi Takenaka; Hiromitsu Hada; Munehiro Tada; Makoto Miyamura; Toshitsugu Sakamoto

  IEEE Embedded Systems Letters, Dec. 2018, Peer-reviewed

  
• Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors

  Y. Masuda; J. Nagayama; H. Takeno; Y. Ogawa; Y. Momiyama; M. Hashimoto

  Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2018, Peer-reviewed

  
• Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA

  R. Doi; J. Yu; M. Hashimoto

  Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2018, Peer-reviewed

  
• Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving

  Y. Masuda; T. Onoye; M. Hashimoto

  IEEE Transactions on VLSI Systems, Nov. 2018, Peer-reviewed

  
• Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams

  M. Hashimoto; W. Liao; S. Manabe; Y. Watanabe

  Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2018, Invited

  
• Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs

  S. Abe; W. Liao; S. Manabe; T. Sato; M.Hashimoto; Y. Watanabe

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2018, Peer-reviewed

  
• Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM

  W. Liao; M. Hashimoto; S. Manabe; S. Abe; Y. Watanabe

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2018, Peer-reviewed

  
• Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs

  S. Manabe; Y; Watanabe; W. Liao; M. Hashimoto; S. Abe

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2018, Peer-reviewed

  
• Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk SRAMs

  W. Liao; M. Hashimoto; S. Manabe; Y. Watanabe; K. Nakano; H. Sato; T. Kin; K. Hamada; M. Tampo; Y. Miyake

  IEEE Transactions on Nuclear Science, Sep. 2018, Peer-reviewed

  
• Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs

  S. Manabe; Y. Watanabe; W. Liao; M. Hashimoto; K. Nakano; H. Sato; T. Kin; S. Abe; K. Hamada; M. Tampo; Y. Miyake

  IEEE Transactions on Nuclear Science, Sep. 2018, Peer-reviewed

  
• FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化

  金本俊幾; 葛西孝己; 今井雅; 黒川敦; 橋本昌宜; 陳俊; 神藤始

  情報処理学会DAシンポジウム, Aug. 2018

  
• エラー予告FFとレプリカの電圧マージン制御性能の定量的比較

  増田豊; 長山準; 武野紘宜; 小川芳正; 籾山陽一; 橋本昌宜

  情報処理学会DAシンポジウム, Aug. 2018

  
• ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法

  土井龍太郎; 劉載勲; 橋本昌宜

  情報処理学会DAシンポジウム, Aug. 2018

  
• Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks

  K. Itoh; J. Yu; M. Hashimoto

  Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC), Aug. 2018, Peer-reviewed

  
• Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs

  Seiya Manabe; Yukinobu Watanabe; Wang Liao; Masanori Hashimoto; Keita Nakano; Hikaru Sato; Tadahiro Kin; Shin Ichiro Abe; Koji Hamada; Motonobu Tampo; Yasuhiro Miyake

  IEEE Transactions on Nuclear Science, Aug. 2018, Peer-reviewed

  
• Interconnect Delay Analysis for RRAM Crossbar Based FPGA

  M. Hashimoto; Y. Nakazawa; R. Doi; J. Yu

  Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul. 2018, Peer-reviewed, Invited

  
• SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA

  R. Doi; M. Hashimoto

  Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul. 2018, Peer-reviewed

  
• A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes

  R. Shirai; T. Hirose; M. Hashimoto

  Proceedings of International NEWCAS Conference, Jun. 2018, Peer-reviewed

  
• VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units

  L. Zhang; B. Li; M. Hashimoto; U. Schlichtmann

  Proceedings of Design Automation Conference (DAC), Jun. 2018, Peer-reviewed

  
• MTTF-aware design methodology for adaptive voltage scaling

  Masanori Hashimoto; Yutaka Masuda

  China Semiconductor Technology International Conference 2018, CSTIC 2018, 29 May 2018, Peer-reviewed, Invited

  
• Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties

  Kuen-Wey Lin; Masanori Hashimoto; Yih-Lang Li

  Proceedings - International Symposium on Quality Electronic Design, ISQED, 09 May 2018, Peer-reviewed

  
• An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency

  J. Chen; T; Kanamoto; H. Kando; M. Hashimoto

  Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018, Peer-reviewed

  
• Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature

  T. Nakayama; M. Hashimoto

  Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2018, Peer-reviewed

  
• 過電圧スケーリングを用いた不正確計算による消費電力削減の検討

  佐藤雅紘; 増田豊; 橋本昌宜

  電子情報通信学会VLSI設計技術研究会, Mar. 2018

  
• ビアスイッチFPGA向け配線遅延解析手法の検討

  中澤祐希; 土井龍太郎; 劉載勲; 橋本昌宜

  電子情報通信学会 VLSI設計技術研究会, Mar. 2018

  
• MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits

  Yutaka Masuda; Masanori Hashimoto

  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 20 Feb. 2018, Peer-reviewed

  
• 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築

  葛西孝己; 神藤始; 陳俊; 橋本昌宜; 今井雅; 黒川敦; 金本俊幾

  情報処理学会 東北支部研究会, Feb. 2018

  
• From process variations to reliability: A survey of timing of digital circuits in the nanometer era

  Bing Li; Masanori Hashimoto; Ulf Schlichtmann

  IPSJ Transactions on System LSI Design Methodology, 01 Feb. 2018, Peer-reviewed, Invited

  
• An analytic evaluation on soft error immunity enhancement due to temporal triplication

  Ryutaro Doi; Masanori Hashimoto; Takao Onoye

  International Journal of Embedded Systems, 2018, Peer-reviewed

  
• A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes

  Ryo Shirai; Tetsuya Hirose; Masanori Hashimoto

  2018 16TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2018, Peer-reviewed

  
• Dedicated antenna less power efficient OOK transmitter for mm-cubic IoT nodes

  Ryo Shirai; Tetsuya Hirose; Masanori Hashimoto

  European Microwave Week 2017: "A Prime Year for a Prime Event", EuMW 2017 - Conference Proceedings; 47th European Microwave Conference, EuMC 2017, 19 Dec. 2017, Peer-reviewed

  
• IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発

  白井僚; 廣瀬哲也; 橋本昌宜

  電子情報通信学会 集積回路研究会, Dec. 2017, Peer-reviewed

  
• 近傍界磁界通信・電界測距共用mm3級アンテナの実装と評価

  白井僚; 河野仁; 廣瀬哲也; 橋本昌宜

  電子情報通信学会 回路とシステム研究会, Dec. 2017

  
• 高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発

  橋本昌宜

  電気関連学会関西連合大会, Nov. 2017, Invited

  
• Multiple sensitive volume based soft error rate estimation with machine learning

  Soichi Hirokawa; Ryo Harada; Kenshiro Sakuta; Yukinobu Watanabe; Masanori Hashimoto

  Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 31 Oct. 2017, Peer-reviewed

  
• Soft error rate estimation with TCAD and machine learning

  Masanori Hashimoto; Wang Liao; Soichi Hirokawa

  International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 25 Oct. 2017, Invited

  
• Momentum and Supply Voltage Dependencies of SEUs Induced by Low-energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs

  S. Manabe; Y; Watanabe; W. Liao; M. Hashimoto; K. Nakano; H. Sato; T. Kin; K. Hamada; M. Tampo; Y. Miyake

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Oct. 2017, Peer-reviewed

  
• Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs

  W. Liao; M. Hashimoto; S. Manabe; Y. Watanabe; K; Nakano; H. Sato; T. Kin; K. Hamada; M. Tampo; Y. Miyake

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Oct. 2017, Peer-reviewed

  
• Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node

  Ryo Shirai; Jin Kono; Tetsuya Hirose; Masanori Hashimoto

  Proceedings - IEEE International Symposium on Circuits and Systems, 25 Sep. 2017, Peer-reviewed

  
• Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V - Bulk v

  Liao Wang; Soichi Hirokawa; Ryo Harada; Masanori Hashimoto

  Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, 11 Aug. 2017, Peer-reviewed

  
• 常温で論理テスト可能な超低温動作VLSIのタイミング設計法の検討

  中山貴博; 橋本昌宜

  情報処理学会DAシンポジウム, Aug. 2017

  
• エラー予告ベース適応的電圧制御のMTTF考慮設計手法

  増田豊; 橋本昌宜

  情報処理学会DAシンポジウム, Aug. 2017

  
• 容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築

  金本俊幾; 葛西孝己; 今井雅; 黒川敦; 橋本昌宜; 陳俊; 神藤始

  情報処理学会DAシンポジウム, Aug. 2017

  
• ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証

  土井龍太郎; 橋本 昌宜

  情報処理学会DAシンポジウム, Aug. 2017

  
• Near-future traffic evaluation based navigation for automated driving vehicles

  Kuen-Wey Lin; Yih-Lang Li; Masanori Hashimoto

  IEEE Intelligent Vehicles Symposium, Proceedings, 28 Jul. 2017, Peer-reviewed

  
• Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes

  Masanori Hashimoto; Ryo Shirai; Yuichi Itoh; Tetsuya Hirose

  Proceedings of International Conference on ASIC, 01 Jul. 2017, Peer-reviewed

  
• Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors

  Yutaka Masuda; Takao Onoye; Masanori Hashimoto

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jul. 2017, Peer-reviewed

  
• Minimizing detection-to-boosting latency toward low-power error-resilient circuits

  Chih-Cheng Hsu; Masanori Hashimoto; Mark Po-Hung Lin

  INTEGRATION-THE VLSI JOURNAL, Jun. 2017, Peer-reviewed

  
• GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction

  K. Hirosue; S. Ukawa; Y. Itoh; T. Onoye; M. Hashimoto

  Proceedings of International Conference on Intelligent User Interfaces (IUI), Mar. 2017, Peer-reviewed

  
• 低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証

  伴野直樹; 多田宗弘; 岡本浩一郎; 井口憲幸; 阪本利司; 波田博光; 越智裕之; 小野寺秀俊; 橋本昌宜; 杉林直彦

  電子情報通信学会シリコン材料・デバイス研究会, Feb. 2017, Invited

  
• 50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic

  N. Banno; M. Tilda; K. Okamoto; N. Iguchi; T. Sakamoto; H. Hada; H. Ochi; H. Onodera; M. Hashimoto; T. Sugibayashi

  Technical Digest - International Electron Devices Meeting, IEDM, 31 Jan. 2017, Peer-reviewed

  
• 容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築

  葛西 孝己; 今井 雅; 黒川 敦; 金本 俊幾; 陳 俊; 橋本 昌宜; 神藤 始

  電気関係学会東北支部連合大会講演論文集, 2017

  
• Near-Field Dual-Use Antenna for Magnetic-Field based Communication and Electrical-Field based Distance Sensing in mm(3)-Class Sensor Node

  Ryo Shirai; Jin Kono; Tetsuya Hirose; Masanori Hashimoto

  2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, Peer-reviewed

  
• Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices

  Sota Masuda; Tetsuya Hirose; Yuki Akihara; Nobutaka Kuroki; Masahiro Numa; Masanori Hashimoto

  2017 IEEE WIRELESS POWER TRANSFER CONFERENCE (WPTC 2017), 2017, Peer-reviewed

  
• Critical path isolation for time-to-failure extension and lower voltage operation.

  Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  Proceedings of the 35th International Conference on Computer-Aided Design(ICCAD), Nov. 2016, Peer-reviewed

  
• Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms

  Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 20 Oct. 2016, Peer-reviewed

  
• 確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察

  佐藤雅紘; 増田豊; 飯塚翔一; 尾上孝雄; 橋本昌宜

  Sep. 2016

  
• 低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法

  増田豊; 尾上孝雄; 橋本昌宜

  Sep. 2016

  
• A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.

  Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto

  26th International Conference on Field Programmable Logic and Applications(FPL), Sep. 2016, Peer-reviewed

  
• Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning

  S. Hirokawa; R. Harada; K. Sakuta; Y. Watanabe; M. Hashimoto

  Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep. 2016, Peer-reviewed

  
• 超低電圧SRAMのソフトエラー耐性

  橋本昌宜

  Aug. 2016, Invited

  
• Novel processor architecture for onboard infrared sensors

  H. Hihara; A. Iwasaki; N. Tamagawa; M. Kuribayashi; M. Hashimoto; Y. Mitsuyama; H. Ochi; H. Onodera; H. Kanbara; K. Wakabayashi; T. Sugibayashi

  Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, Aug. 2016, Invited

  
• Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits

  Chih-Cheng Hsu; Mark Po-Hung Lint; Masanori Hashimoto

  Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016, 04 Jun. 2016, Peer-reviewed

  
• Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits

  C.-C. Hsu; M; P.-H. Lin; M. Hashimoto

  Proceedings of System Level Interconnect Prediction (SLIP) Workshop, Jun. 2016, Peer-reviewed

  
• Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation

  Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2016, Peer-reviewed

  
• Hardware-Simulation Correlation of Timing Error Detection Performance of Software-based Error Detection Mechanisms

  Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 2016, Peer-reviewed

  
• 50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch for a highly-dense Reconfigurable Logic

  N. Banno; M. Tada; K. Okamoto; N. Iguchi; T. Sakamoto; H. Hada; H. Ochi; H. Onodera; M. Hashimoto; T. Sugibayashi

  2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016, Peer-reviewed

  
• Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes

  Souta Masuda; Tetsuya Hirose; Yuki Akihara; Nobutaka Kuroki; Masahiro Numa; Masanori Hashimoto

  2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 2016, Peer-reviewed

  
• Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems

  Yuki Akihara; Tetsuya Hirose; Sota Masuda; Nobutaka Kuroki; Masahiro Numa; Masanori Hashimoto

  2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 2016, Peer-reviewed

  
• A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect using Via-switch

  Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto

  2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2016, Peer-reviewed

  
• Novel processor architecture for onboard infrared sensors

  Hiroki Hihara; Akira Iwasaki; Nobuo Tamagawa; Mitsunobu Kuribayashi; Masanori Hashimoto; Yukio Mitsuyama; Hiroyuki Ochi; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Munehiro Tada

  INFRARED REMOTE SENSING AND INSTRUMENTATION XXIV, 2016, Invited

  
• Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator

  Shoichi Iizuka; Yuma Higuchi; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2015, Peer-reviewed

  
• Proximity distance estimation based on electric field communication between 1 mm(3) sensor nodes

  Tatsuya Shinada; Masanori Hashimoto; Takao Onoye

  ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, Dec. 2015, Peer-reviewed

  
• A Novel Two-Varistors (a-Si/SiN/a-Si) selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-outs

  N. Banno; M.Tada; K. Okamoto; N. Iguchi; T. Sakamoto; M. Miyamura; Y. Tsuji; H. Hada; H. Ochi; H. Onodera; M. Hashimoto; T. Sugibayashi

  2015 International Electron Devices Meeting, Dec. 2015, Peer-reviewed

  
• A wireless power transfer system for small-sized sensor applications

  AKIHARA Yuki; HIROSE Tetsuya; TANAKA Yuki; KUROKI Nobutaka; NUMA Masahiro; HASHIMOTO Masanori

  Extended abstract of the 2015 international conference on solid state devices and materials, Sep. 2015, Peer-reviewed

  
• 電源ノイズ起因タイミング故障のデバッグにおけるC 言語ベース故障検出 手法の有効性評価

  増田豊; 橋本昌宜; 尾上孝雄

  情報処理学会DA シンポジウム2015論文集, Aug. 2015

  
• 小型センサデバイスに向けた無線給電システムの設計

  AKIHARA Yuki; HIROSE Tetsuya; TANAKA Yuki; KUROKI Nobutaka; NUMA Masahiro; HASHIMOTO Masanori

  第28回 回路とシステムワークショップ, Aug. 2015, Peer-reviewed

  
• Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs

  Soichi Hirokawa; Ryo Harada; Masanori Hashimoto; Takao Onoye

  IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Apr. 2015, Peer-reviewed

  
• Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator

  Shoichi Iizuka; Yuma Higuchi; Masanori Hashimoto; Takao Onoye

  2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, Peer-reviewed

  
• Real-time On-chip Supply Voltage Sensor and Its Application to Trace-based Timing Error Localization

  Miho Ueno; Masanori Hashimoto; Takao Onoye

  2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2015, Peer-reviewed

  
• Stochastic Timing Error Rate Estimation under Process and Temporal Variations

  Shoichi Iizuka; Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  2015 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2015, Peer-reviewed

  
• Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise

  Yutaka Masuda; Masanori Hashimoto; Takao Onoye

  2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2015, Peer-reviewed

  
• Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

  Masanori Hashimoto; Dawood Alnajjar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera

  The 20th Asia South-Pacific Design Automation Conference, Jan. 2015, Peer-reviewed

  
• A Process and Temperature Tolerant Oscillator-Based True Random Number Generator

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2014, Peer-reviewed

  
• Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

  Hiroaki Konoura; Dawood Alnajjar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2014, Peer-reviewed

  
• Performance Evaluation of Software-based Quick Error Detection Technique for Localizing Electrical Failures due to Dynamic Power Supply Noise

  増田豊; 橋本昌宜; 尾上孝雄

  情報処理学会DA シンポジウム2014論文集, Aug. 2014

  
• NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time

  Hiroaki Konoura; Toshihiro Kameda; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jul. 2014, Peer-reviewed

  
• SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

  Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jul. 2014, Peer-reviewed

  
• Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices

  Hiroaki Konoura; Takashi Imagawa; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jul. 2014, Peer-reviewed

  
• 経時劣化概説(招待)

  佐藤高史; 橋本 昌宜

  日本信頼性学会誌, Dec. 2013, Peer-reviewed, Invited

  
• Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing

  D. Alnajjar; H. Konoura; Y. Mitsuyama; H. Shimada; K. Kobayashi; H. Kanbara; H. Ochi; T. Imagawa; S. Noda; K. Wakabayashi; M. Hashimoto; T. Onoye; H. Onodera

  Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Nov. 2013, Peer-reviewed

  
• Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices

  Toshihiro Kameda; Hiroaki Konoura; Dawood Alnajjar; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Aug. 2013, Peer-reviewed

  
• A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling

  Takehiko Amaki; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, Aug. 2013, Peer-reviewed

  
• 動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討

  郡浦 宏明; 今川 隆司; 密山 幸男; 橋本 昌宜; 尾上 孝雄

  電子情報通信学会技術研究報告, Vol.113, No.52, 13 May 2013

  
• Supply Noise Suppression by Triple-Well Structure

  Yasuhiro Ogasahara; Masanori Hashimoto; Toshiki Kanamoto; Takao Onoye

  IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Apr. 2013, Peer-reviewed

  
• Jitter Amplifier for Oscillator-Based True Random Number Generator

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Mar. 2013, Peer-reviewed

  
• Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling

  Igors Homjakovs; Masanori Hashimoto; Tetsuya Hirose; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Feb. 2013, Peer-reviewed

  
• Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing

  Shoichi Iizuka; Masafumi Mizuno; Dan Kuroda; Masanori Hashimoto; Takao Onoye

  2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2013, Peer-reviewed

  
• Proximity Distance Estimation based on Capacitive Coupling between 1mm(3) Sensor Nodes

  Tatsuya Shinada; Masanori Hashimoto; Takao Onoye

  2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2013, Peer-reviewed

  
• A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation

  Igors Homjakovs; Tetsuya Hirose; Yuji Osaki; Masanori Hashimoto; Takao Onoye

  IEICE Electronics Express, 2013

  
• Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure

  Yasumichi Takai; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2012, Peer-reviewed

  
• A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning

  Shuta Kimura; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2012, Peer-reviewed

  
• Power Distribution Network Optimization for Timing Improvement With Statistical Noise Model and Timing Analysis

  T. Enami; T. Sato; M. Hashimoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2012, Peer-reviewed

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• Adaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits

  Fuketa, H.; Hashimoto, M.; Mitsuyama, Y.; Onoye, T.

  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2012, Peer-reviewed

  
• Static Voltage Over-scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices

  Dawood Alnajjar; Masanori Hashimoto; Takao Onoye; Yukio Mitsuyama

  2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2012, Peer-reviewed

  
• Body Bias Clustering for Low Test-Cost Post-Silicon Tuning

  Shuta Kimura; Masanori Hashimoto; Takao Onoye

  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2012, Peer-reviewed

  
• Signal-dependent analog-to-digital converter based on MINIMAX sampling

  Igors Homjakovs; Masanori Hashimoto; Takao Onoye; Tetsuya Hirose

  ISOCC 2012 - 2012 International SoC Design Conference, 2012, Peer-reviewed

  
• Stress Probability Computation for Estimating NBTI-Induced Delay Degradation

  Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2011, Peer-reviewed

  
• Extracting Device-Parameter Variations with RO-Based Sensors

  Ken-ichi Shinkai; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2011, Peer-reviewed

  
• Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Aug. 2011, Peer-reviewed

  
• An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion

  Hiroshi Fuketa; Dan Kuroda; Masanori Hashimoto; Takao Onoye

  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, May 2011, Peer-reviewed

  
• Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure

  Yasumichi Takai; Masanori Hashimoto; Takao Onoye

  2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011, Peer-reviewed

  
• A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling

  Takehiko Amaki; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  INFORMATION SECURITY APPLICATIONS, 2011, Peer-reviewed

  
• Jitter Amplifier for Oscillator-Based True Random Number Generator

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011, Peer-reviewed

  
• An Oscillator-Based True Random Number Generator with Jitter Amplifier

  Takehiko Amaki; Masanori Hashimoto; Takao Onoye

  2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, Peer-reviewed

  
• Signal-dependent analog-to-digital conversion based on MINIMAX sampling

  Igors Homjakovs; Masanori Hashimoto; Takao Onoye; Tetsuya Hirose

  Midwest Symposium on Circuits and Systems, 2011, Peer-reviewed

  
• Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

  Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2010, Peer-reviewed

  
• Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Jul. 2010, Peer-reviewed

  
• Impact of Self-heating in Wire Interconnection on Timing

  T. Kanamoto; T. Okumura; K. Furukawa; H. Takafuji; A. Kurokawa; K. Hachiya; T. Sakata; M. Tanaka; H. Nakashima; H. Masuda; T. Sato; M. Hashimoto

  IEICE Transactions on Electronics, Mar. 2010, Peer-reviewed

  
• Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

  Huang, Z.; Kurokawa, A.; Hashimoto, M.; Sato, T.; Jiang, M.; Inoue, Y.

  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb. 2010, Peer-reviewed

  
• Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration

  Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye

  PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 2010, Peer-reviewed

  
• Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2010, Peer-reviewed

  
• Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEICE Transactions, Dec. 2009, Peer-reviewed

  
• An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability

  T. Sakata; T. Okumura; A. Kurokawa; H. Nakashima; H. Masuda; T. Sato; M. Hashimoto; K. Hachiya; K. Furukawa; M. Tanaka; H. Takafuji; T. Kanamoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2009, Peer-reviewed

  
• Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, Sep. 2009, Peer-reviewed

  
• Interconnect Modeling: A Physical Design Perspective (Invited)

  A. Kurokawa; T. Sato; T. Kanamoto; M. Hashimoto

  IEEE Transactions on Electron Devices, Sep. 2009, Peer-reviewed, Invited

  
• All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

  Ogasahara Yasuhiro; Hashimoto Masanori; Onoye Takao

  IEEE JOURNAL OF SOLID-STATE CIRCUITS, Jun. 2009, Peer-reviewed

  
• Reduction approach of leak current variation due to process variation

  佐方剛; 黒川敦; 奥村隆昌; 中島英斉; 増田弘生; 佐藤高史; 橋本昌宜; 蜂屋孝太郎; 古川且洋; 田中正和; 高藤浩資; 金本俊幾

  IEICE (Karuizawa) Workshop on Circuits and Systems, Apr. 2009, Peer-reviewed

  
• Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

  T. Okumura; A. Kurokawa; H. Masuda; T. Kanamoto; M. Hashimoto; H. Takafuji; H. Nakashima; N. Ono; T. Sakata; T. Sato

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2009, Peer-reviewed

  
• An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability

  Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEICE TRANSACTIONS ON ELECTRONICS, Feb. 2009, Peer-reviewed

  
• Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits

  Koichi Hamamoto; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  ISLPED 09, 2009, Peer-reviewed

  
• Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction

  Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2009, Peer-reviewed

  
• Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution

  Shinya Abe; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2008, Peer-reviewed

  
• Area-Efficient Reconfigurable Architecture for Media Processing

  Yukio Mitsuyama; Kazuma Takahashi; Rintaro Imai; Masanori Hashimoto; Takao Onoye; Isao Shirakawa

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2008, Peer-reviewed

  
• Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.

  Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye

  ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2008, Peer-reviewed

  
• Analysis of output transition time variation due to Vth variations

  奥村隆昌; 黒川敦; 増田弘生; 金本俊幾; 佐藤高史; 橋本昌宜; 高藤浩資; 中島英斉; 小野信任

  IEICE (Workshop) on Circuits and Systems, Apr. 2008, Peer-reviewed

  
• Measurement and analysis of inductive coupling noise in 90 nm global interconnects

  Ogasahara Yasuhiro; Hashimoto Masanori; Onoye Takao

  IEEE JOURNAL OF SOLID-STATE CIRCUITS, Mar. 2008, Peer-reviewed

  
• Timing Analysis Considering Temporal Supply Voltage Fluctuation

  M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera

  IEICE Transactions on Information and Systems, Mar. 2008, Peer-reviewed

  
• Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process

  Yasuhiro Ogasahara; Masanori Hashimoto; Toshiki Kanamoto; Takao Onoye

  2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 2008, Peer-reviewed

  
• Clock Skew evaluation considering manufacturing variability in mesh-style clock distribution

  Shinya Abe; Masanori Hashimoto; Takao Onoye

  ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, Peer-reviewed

  
• Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, Peer-reviewed

  
• Timing analysis considering spatial power/ground level variation

  M. Hashimoto; J. Yamaguchi; H. Onodera

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2007, Peer-reviewed

  
• Optimal termination of on-chip transmission-lines for high-speed signaling

  Tsuchiya, Akira; Hashimoto, Masanori; Onodera, Hidetoshi

  IEICE TRANSACTIONS ON ELECTRONICS, Jun. 2007, Peer-reviewed

  
• Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design

  T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto

  Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006, May 2007, Peer-reviewed

  
• Quantitative prediction of on-chip capacitive and inductive crosstalk noise and tradeoff between wire cross-sectional area and inductive crosstalk effect

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Apr. 2007, Peer-reviewed

  
• Proposal of Metrics for SSTA Accuracy Evaluation

  H. Kobayashi; N. Ono; T. Sato; J. Iwai; H. Nakashima; T. Okumura; M. Hashimoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Apr. 2007, Peer-reviewed

  
• Quantitative prediction of on-chip capacitive and inductive crosstalk noise and discussion on wire cross-sectional area toward inductive crosstalk free interconnects

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2007, Peer-reviewed

  
• Dynamic supply noise measurement with all digital gated oscillator for evaluating decoupling capacitance effect

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, Peer-reviewed

  
• Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement

  Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato; Takao Onoye

  IEEE Transactions on Circuits and Systems II: Express Briefs, 2007, Peer-reviewed

  
• Special section on VLSI Design and CAD Algorithms

  Hidetoshi Onodera; Makoto Ikeda; Tohru Ishihara; Tsuyoshi Isshiki; Koji Inoue; Kenichi Okada; Seiji Kajihara; Mineo Kaneko; Hiroshi Kawaguchi; Shinji Kimura; Morihiro Kuga; Atsushi Kurokawa; Takashi Sato; Toshiyuki Shibuya; Yoichi Shiraishi; Kazuyoshi Takagi; Atsushi Takahashi; Yoshinori Takeuchi; Nozomu Togawa; Hiroyuki Tomiyama; Yuichi Nakamura; Kiyoharu Hamaguchi; Yukiya Miura; Shin Ichi Minato; Ryuichi Yamaguchi; Masaaki Yamada; Yasushi Yuminaka; Takayuki Watanabe; Masanori Hashimoto; Masayuki Miyazaki

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2006

  
• Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design

  T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2006, Peer-reviewed

  
• Interconnect RL extraction based on transfer characteristics of transmission-line

  Tsuchiya, A.; Hashimoto, M.; Onodera, H.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2006, Peer-reviewed

  
• On-chip Thermal Gradient Analysis Considering Interdependence Between Leakage Power and Temperature

  T. Sato; J. Ichimiya; N. Ono; M. Hashimoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2006, Peer-reviewed

  
• Input capacitance modeling of logic gates for accurate static timing analysis

  T. Kouno; M. Hashimoto; H. Onodera

  2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Nov. 2006, Peer-reviewed

  
• 統計的STAの有効性の検証手法

  小林 宏行; 小野 信任; 佐藤 高史; 岩井 二郎; 橋本 昌宜

  第19回 回路とシステム(軽井沢)ワークショップ, Apr. 2006, Peer-reviewed

  
• 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル

  新開 健一; 橋本 昌宜; 黒川 敦; 尾上 孝雄

  第19回 回路とシステム(軽井沢)ワークショップ, Apr. 2006, Peer-reviewed

  
• LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測

  小笠原 泰弘; 橋本 昌宜; 尾上 孝雄

  第19回 回路とシステム(軽井沢)ワークショップ, Apr. 2006, Peer-reviewed

  
• 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術

  伊地知 孝仁; 橋本 昌宜; 高橋 真吾; 築山 修治; 白川 功

  電子情報通信学会 VLSI設計技術研究会, Mar. 2006

  
• ロードマップに準拠したSPICEトランジスタモデルの構築

  上村 晋一朗; 土谷 亮; 橋本 昌宜; 小野寺 秀俊

  2006年電子情報通信学会総合大会講演論文集, Mar. 2006

  
• 電源ノイズ解析のための回路動作部表現法の評価

  榎並 孝司; 橋本 昌宜; 尾上 孝雄

  2006年電子情報通信学会総合大会講演論文集, Mar. 2006

  
• A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

  Ken'ichi Shinkai; Masanori Hashimoto; Atsushi Kurokawa; Takao Onoye

  IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, Peer-reviewed

  
• Measurement of inductive coupling effect on timing in 90nm global interconnects

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, Peer-reviewed

  
• Interconnect RL extraction at a single representative frequency

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Jan. 2006, Peer-reviewed

  
• A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

  Ken'ichi Shinkai; Masanori Hashimoto; Atsushi Kurokawa; Takao Onoye

  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2006, Peer-reviewed

  
• Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction

  T. Kanamoto; T. Ikeda; A. Tsuchiya; H. Onodera; M. Hashimoto

  International Workshop on Compact Modeling, Jan. 2006, Peer-reviewed

  
• Statistical analysis of clock skew variation in H-tree structure

  M Hashimoto; T Yamamoto; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2005, Peer-reviewed

  
• Effects of on-chip inductance on power distribution grid

  A. Muramatsu; M. Hashimoto; H. Onodera

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

  
• Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.

  Atsushi Kurokawa; Masanori Hashimoto; Akira Kasebe; Zhangcai Huang; Yun Yang; Yasuaki Inoue; Ryosuke Inagaki; Hiroo Masuda

  IEICE Transactions, Dec. 2005, Peer-reviewed

  
• Successive pad assignment for minimizing supply voltage drop

  T. Sato; M. Hashimoto; H. Onodera

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

  
• Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion

  T. Sato; M. Hashimoto; H. Onodera

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

  
• On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design

  T. Sato; J. Ichimiya; N. Ono; K. Hachiya; M. Hashimoto

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2005, Peer-reviewed

  
• CMLを用いたオンチップ長距離高速信号伝送技術の開発

  土谷 亮; 新名 亮規; 橋本 昌宜; 小野寺 秀俊

  第9回システムLSIワークショップ, Nov. 2005

  
• Performance prediction of on-chip high-throughput global signaling

  M. Hashimoto; A. Tsuchiya; A. Shinmyo; H. Onodera

  IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 2005, Peer-reviewed

  
• Design guideline for resistive termination of on-chip high-speed interconnects

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proceedings of the Custom Integrated Circuits Conference, Sep. 2005, Peer-reviewed

  
• Substrate loss of on-chip transmission-lines with power/ground wires in lower layer

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005, May 2005, Peer-reviewed

  
• オンチップ高速信号伝送用線路の解析的性能評価

  土谷亮; 橋本昌宜; 小野寺秀俊

  信学技報, 11 Mar. 2005

  
• A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL

  T. Miyazaki; M. Hashimoto; H. Onodera

  IEICE Transactions on Electronics, Mar. 2005, Peer-reviewed

  
• Statistical analysis of clock skew variation in H-tree structure

  M Hashimoto; T Yamamoto; H Onodera

  6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, Peer-reviewed

  
• オンチップ高速信号伝送における終端抵抗決定手法

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005., 2005, Peer-reviewed

  
• 配線の伝達特性に基づく抽出周波数決定手法

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  DAシンポジウム 2005, pp.169-174, Aug 2005., 2005, Peer-reviewed

  
• Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics

  Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera

  2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005., 2005, Peer-reviewed

  
• Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process

  A. Shinmyo; M. Hashimoto; H. Onodera

  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Jan. 2005, Peer-reviewed

  
• Return path selection for loop RL extraction

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Jan. 2005, Peer-reviewed

  
• Measurement and analysis of delay variation due to inductive coupling

  Y Ogasahara; M Hashimoto; T Onoye

  CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, Peer-reviewed

  
• Timing analysis considering spatial power/ground level variation

  M. Hashimoto; J. Yamaguchi; H. Onodera

  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, Nov. 2004, Peer-reviewed

  
• On-chip global signaling by wave pipelining

  M. Hashimoto; A. Tsuchiya; H. Onodera

  IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 2004, Peer-reviewed

  
• Performance Limitation of On-chip Global Interconnects for High-speed Signaling

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proc. IEEE Custom Integrated Circuits Conference, Oct. 2004, Peer-reviewed

  
• 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価

  金本 俊幾; 阿久津滋聖; 中林 太美世; 一宮 敬弘; 蜂屋 孝太郎; 石川 博; 室本 栄; 小林 宏行; 橋本 昌宜; 黒川 敦

  Jul. 2004

  
• フロアプランにおけるオンチップ熱ばらつきの解析と対策

  佐藤 高史; 市宮 淳次; 小野 信任; 蜂屋 孝太郎; 橋本 昌宜

  Jul. 2004

  
• 配線RL抽出におけるリターンパス選択手法

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Jul. 2004

  
• オンチップインダクタンスを考慮したLSI電源配線網解析

  村松 篤; 橋本 昌宜; 小野寺 秀俊

  Jul. 2004

  
• オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Apr. 2004

  
• Equivalent, waveform propagation for static timing analysis

  M Hashimoto; Y Yamada; H Onodera

  IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Apr. 2004, Peer-reviewed

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• Equivalent Waveform Propagation for Static Timing Analysis

  M. Hashimoto; Y. Yamada; H. Onodera

  IEEE Trans. on CAD, Apr. 2004, Peer-reviewed

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• ゲート毎の電源電圧変動を考慮した静的遅延解析法

  山口 隼司; 橋本 昌宜; 小野寺 秀俊

  Mar. 2004

  
• 電源電圧変動に対するオンチップ配線インダクタンスの影響

  村松 篤; 橋本 昌宜; 小野寺 秀俊

  Mar. 2004

  
• Design and optimization of CMOS current mode logic dividers

  A Shinmyo; M Hashimoto; H Onodera

  PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, Peer-reviewed

  
• Automatic generation of standard cell library in VDSM technologies

  M Hashimoto; K Fujimori; H Onodera

  ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2004, Peer-reviewed

  
• A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

  T Miyazaki; M Hashimoto; H Onodera

  ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, Peer-reviewed

  
• Representative frequency for interconnect R(f)L(f)C extraction

  A Tsuchiya; M Hashimoto; H Onodera

  ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, Peer-reviewed

  
• Representative frequency for interconnect R(f)L(f)C extraction

  A Tsuchiya; M Hashimoto; H Onodera

  ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004

  
• Experimental study on cell-base high-performance datapath design

  M Hashimoto; Y Hayashi; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2003

  
• Crosstalk noise estimation for generic RC trees

  M Hashimoto; M Takahashi; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2003

  
• 電源配線の等価回路簡略化による電源解析高速化の検討

  村松 篤; 橋本 昌宜; 小野寺 秀俊

  Nov. 2003

  
• デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー

  宮崎 崇仁; 橋本 昌宜; 小野寺 秀俊

  Sep. 2003

  
• オンチップ高速信号配線における波形歪みの影響

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Sep. 2003

  
• 直交配線を持つオンチップ伝送線路の特性評価

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Jul. 2003

  
• A Statistical Methodology for Screening Inductance Dominated Interconnects in Timing Analysis

  T. Kanamoto; T. Sato; A. Kurokawa; Y. Kawakami; H. Oka; T. Kitaura; H. Kobayashi; M. Hashimoto

  IPSJ Transactions, May 2003

  
• 配線R(f)L(f)C抽出のための代表周波数決定手法

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Apr. 2003

  
• Frequency Determination for Interconnect RLC Extraction

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proc. Workshop on Synthesis and System Integration of Mixed Technologies, Apr. 2003, Peer-reviewed

  
• Slew Calculation against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis

  Y. Yamada; M. Hashimoto; H. Onodera

  Proc. Workshop on Synthesis and System Integration of Mixed Technologies, Apr. 2003, Peer-reviewed

  
• Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis

  M. Hashimoto; Y. Yamada; H. Onodera

  Proc. ACM/IEEE International Symposium on Physical Design, Apr. 2003, Peer-reviewed

  
• オンチップデカップリング容量の最適寄生抵抗値の決定法

  村松 篤; 橋本 昌宜; 小野寺 秀俊

  Mar. 2003

  
• オンチップオシロ用サンプルホールド回路の広周波数帯域化

  宮崎 崇仁; 新名 亮規; 橋本 昌宜; 小野寺 秀俊

  Mar. 2003

  
• 信号配線と下層配線との結合に対する直交配線の影響

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Mar. 2003

  
• LSI物理設計におけるSignal Integrity問題

  橋本 昌宜

  Mar. 2003, Invited

  
• 静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応--

  山田 祐嗣; 橋本 昌宜; 小野寺 秀俊

  Jan. 2003

  
• Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 mu m technologies

  M Hashimoto; K Fujimori; H Onodera

  ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, Peer-reviewed

  
• Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF

  T Sato; T Kanamoto; A Kurokawa; Y Kawakami; H Oka; T Kitaura; H Kobayashi; M Hashimoto

  ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, Peer-reviewed

  
• Increase in delay uncertainty by performance optimization

  M Hashimoto; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2002

  
• 容量性クロストークを考慮した高精度タイミング解析に関する研究

  山田 祐嗣; 橋本 昌宜; 小野寺 秀俊

  Nov. 2002

  
• インダクタンスに起因する配線遅延変動の統計的予測手法

  佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏行; 橋本昌宜

  Sep. 2002, Invited

  
• 京大版スタンダードセルライブラリ

  橋本 昌宜

  Sep. 2002, Invited

  
• 長距離高速信号伝送を可能にするVLSI配線構造の検討

  平松 大輔; 土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Jul. 2002

  
• IRドロップを考慮した電源線構造の最適化手法

  山口 隼司; 橋本 昌宜; 小野寺 秀俊

  IPSJ Symposium Series, Jul. 2002

  
• 0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法

  金本 俊幾; 佐藤 高史; 黒川 敦; 川上 善之; 岡 宏規; 北浦 智靖; 池内 敦彦; 小林 宏行; 橋本 昌宜

  Jul. 2002

  
• セルベース設計環境を用いた高性能データパス設計法の検討

  林 宙輝; 橋本 昌宜; 小野寺 秀俊

  Jul. 2002

  
• Experimental Study on Cell-Base High-Performance Datapath Design

  Hashimoto, M.; Hayashi, Y.; Onodera, H.

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2003, Peer-reviewed

  
• Driver Sizing for High-Performace Interconnects Considering Transmission-Line Effects

  A. Tsuchiya; M. Hashimoto; H. Onodera

  IPSJ Transactions, May 2002

  
• インダクタンスが配線遅延に及ぼす影響の定量的評価方法

  佐藤高史; 金本俊幾; 黒川敦; 川上善之; 岡宏規; 北浦智靖; 池内敦彦; 小林宏行; 橋本昌宜

  Apr. 2002

  
• Crosstalk Noise Optimization by Post-Layout Transistor Sizing

  M. Hashimoto; M. Takahashi; H. Onodera

  Proc. ACM/IEEE International Symposium on Physical Design, Apr. 2002, Peer-reviewed

  
• 駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発

  藤森 一憲; 橋本 昌宜; 小野寺 秀俊

  Mar. 2002

  
• LSI配線インダクタンスに対する直交配線の影響

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Mar. 2002

  
• ゲート出力波形導出時の誤差要因とその影響の評価

  山田 祐嗣; 橋本 昌宜; 小野寺 秀俊

  Mar. 2002

  
• Interconnect structures for high-speed long-distance signal transmission

  M Hashimoto; D Hiramatsu; A Tsuchiya; H Onodera

  15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, Peer-reviewed

  
• Post-layout transistor sizing for power reduction in cell-base design

  M Hashimoto; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Nov. 2001, Peer-reviewed

  
• ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法

  橋本 昌宜; 高橋 正郎; 小野寺 秀俊

  Nov. 2001

  
• Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects

  A. Tsuchiya; M. Hashimoto; H. Onodera

  Proc. Workshop on Synthesis and System Integration of Mixed Technologies, Oct. 2001, Peer-reviewed

  
• ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法

  橋本 昌宜; 高橋 正郎; 小野寺 秀俊

  Sep. 2001

  
• 波形重ね合せによるクロストーク遅延変動量の見積もり手法

  高橋 正郎; 橋本 昌宜; 小野寺 秀俊

  Sep. 2001

  
• 長距離高速配線における RC モデルに基づく回路設計の限界

  土谷 亮; 橋本 昌宜; 小野寺 秀俊

  Sep. 2001

  
• 隣接位置を考慮した解析的クロストークノイズ見積もり手法

  高橋 正郎; 橋本 昌宜; 小野寺 秀俊

  Jul. 2001

  
• Increase in delay uncertainty by performance optimization

  M. Hashimoto; H. Onodera

  Proceedings - IEEE International Symposium on Circuits and Systems, May 2001, Peer-reviewed

  
• Increase in Delay Uncertainty by Performance Optimization

  M. Hashimoto; H. Onodera

  Proc. IEEE International Symposium on Circuits and Systems, May 2001, Peer-reviewed

  
• 隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---

  高橋 正郎; 橋本 昌宜; 小野寺 秀俊

  Mar. 2001

  
• 隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用---

  橋本 昌宜; 高橋 正郎; 小野寺 秀俊

  Mar. 2001

  
• Post-layout transistor sizing for power reduction in cell-based design

  M Hashimoto; H Onodera

  PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001

  
• Crosstalk noise estimation for generic RC trees

  M Takahashi; M Hashimoto; H Onodera

  2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, Peer-reviewed

  
• ASIC design methodology with on-demand library generation

  H Onodera; M Hashimoto; T Hashimoto

  2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, Peer-reviewed

  
• Post-layout transistor sizing for power reduction in cell-based design

  M Hashimoto; H Onodera

  PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, Peer-reviewed

  
• A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing

  M. Hashimoto; H. Onodera

  Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Dec. 2000, Peer-reviewed

  
• A performance optimization method by gate resizing based on statistical static timing analysis

  M Hashimoto; H Onodera

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Dec. 2000

  
• パスバランス回路における遅延不確かさの統計的解析

  橋本 昌宜; 小野寺 秀俊

  Nov. 2000

  
• オンデマンドライブラリを用いた最適LSI設計手法

  橋本 昌宜

  Sep. 2000, Invited

  
• パスバランス回路における遅延不確かさの統計的解析

  橋本 昌宜; 小野寺 秀俊

  Sep. 2000

  
• セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法

  橋本 昌宜; 小野寺 秀俊

  Jul. 2000

  
• 静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法

  橋本 昌宜; 小野寺 秀俊

  Apr. 2000

  
• A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis

  M. Hashimoto; H. Onodera

  Proc. Workshop on Synthesis and System Integration of Mixed Technologies, Apr. 2000, Peer-reviewed

  
• A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis

  M. Hashimoto; H. Onodera

  Proc. ACM International Symposium on Physical Design, Apr. 2000, Peer-reviewed

  
• オンデマンドライブラリを用いたシステムLSI詳細設計手法

  橋本 昌宜; 橋本鉄太郎; 西川亮太; 福田大輔; 黒田慎介; 菅俊介; 神原弘之; 小野寺 秀俊

  Mar. 2000

  
• 静的統計遅延解析を用いた最悪遅延時間計算手法

  橋本 昌宜; 小野寺 秀俊

  Mar. 2000

  
• Vector quantization processor for mobile video communication

  T Iwahashi; T Shibayama; M Hashimoto; K Kobayashi; H Onodera

  13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2000, Peer-reviewed

  
• オンデマンドライブラリを用いたシステムLSI詳細設計手法

  Masanori Hashimoto; Tetsutaro Hashimoto; Ryota Nishikawa; Daisuke Fukuda; Shinsuke Kuroda; Syunsuke Suga; Hiroyuki Kanbara; Hidetoshi Onodera

  第3回システムLSI琵琶湖ワークショップ予稿集, 01 Nov. 1999

  
• オンデマンドライブラリを用いたシステムLSI詳細設計手法

  橋本 昌宜; 橋本 鉄太郎; 西川 亮太; 福田 大輔; 黒田 慎介; 菅 俊介; 神原 弘之; 小野寺 秀俊

  Nov. 1999

  
• スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討

  橋本 昌宜; 小野寺 秀俊

  Sep. 1999

  
• A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design

  M. Hashimoto; H. Onodera; K. Tamaru

  Proc. IEEE/ACM Design Automation Conference, Jun. 1999, Peer-reviewed

  
• A Power Optimization Method Considering Glitch Reduction by Gate Sizing

  M. Hashimoto; H. Onodera; K. Tamaru

  IPSJ Transactions, Apr. 1999

  
• A power and delay optimization method using input reordering in cell-based CMOS circuits

  M Hashimoto; H Onodera; K Tamaru

  IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Jan. 1999, Peer-reviewed

  
• グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---

  橋本 昌宜; 小野寺 秀俊; 田丸 啓吉

  Sep. 1998

  
• グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法

  橋本 昌宜; 小野寺 秀俊; 田丸 啓吉

  Jul. 1998

  
• 論理シミュレーションを用いた消費電力見積もりの高精度化手法

  橋本 昌宜; 小野寺 秀俊; 田丸 啓吉

  Mar. 1998

  
• A power optimization method considering glitch reduction by gate sizing

  M Hasimoto; H Onodera; K Tamaru

  1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 1998, Peer-reviewed

  
• 入力端子接続最適化による遅延時間と消費電力の最適化手法

  橋本 昌宜; 小野寺 秀俊; 田丸 啓吉

  Sep. 1997

  
• 入力端子接続最適化による消費電力削減手法

  橋本 昌宜; 小野寺 秀俊; 田丸 啓吉

  Jul. 1997

  
• Input reordering for power and delay optimization

  M Hashimoto; H Onodera; K Tamaru

  TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 1997, Peer-reviewed

  

Misc.

• All Digital Gated Oscillator for Dynamic Supply Noise Measurement

  OGASAHARA Yasuhiro; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 11 Apr. 2008

  
• On Evaluation Methods of nMOS Level Shifter Circuits

  OTSU Makoto; TAKAHASHI Shingo; TSUKIYAMA Shuji; HASHIMOTO Masanori; SHIRAKAWA Isao

  情報処理学会研究報告システムLSI設計技術（SLDM）, 28 Mar. 2008

  
• A-3-5 Evaluation of Clock Skew in Mesh Style Clock Distribution

  Abe Shinya; Hashimoto Masanori; Onoye Takao

  Proceedings of the IEICE General Conference, 07 Mar. 2007

  
• A-3-9 Eye-pattern Evaluation of On-chip Interconnects with Intentional Shunt Conductance

  Jangsombatsiri Siriporn; Hashimoto Masanori; Tsuchiya Akira; Zhu Haikun; Cheng Chung-Kuan

  Proceedings of the IEICE General Conference, 07 Mar. 2007

  
• A-3-6 Area Efficiency Evaluation of Body-biasing Layout Styles for Low Voltage Circuits

  Hamamoto Koichi; Hashimoto Masanori; Mitsuyama Yukio; Onoye Takao

  Proceedings of the IEICE General Conference, 07 Mar. 2007

  
• A-3-10 Adaptive Spatial Division for Statistical Modeling of Power Supply Noise

  Enami Takashi; Hashimoto Masanori

  Proceedings of the Society Conference of IEICE, 2007

  
• A-3-17 A study on design policy for subthreshold circuits with adders

  Fuketa Hiroshi; Hashimoto Masanori; Mitsuyama Yukio; Onoye Takao

  Proceedings of the IEICE General Conference, 2007

  
• VLSI Timing Verification Considering Delay Variation(JISSO Innovation via Design CAE)

  HASHIMOTO Masanori

  Journal of Japan Institute of Electronics Packaging, 01 May 2008

  
• Superposition effect validation of inductive coupling noise based on measurement of interconnect delay variation

  OGASAHARA Yasuhiro; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 06 Mar. 2008

  
• On an Optimality of a Sampling Circuit for Liquid Crystal Displays

  TAKAHASHI Shingo; TSUKIYAMA Shuji; HASHIMOTO Masanori; SHIRAKAWA Isao

  IEICE technical report, 02 Mar. 2007

  
• A-3-14 Future Prediction of Self-heating in Short Intra-block Wires

  Shinkai Kenichi; Hashimoto Masanori; Onoye Takao

  Proceedings of the Society Conference of IEICE, 07 Sep. 2006

  
• Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

  TSUCHIYA Akira; HASHIMOTO Masanori; ONODERA Hidetoshi

  IEICE transactions on fundamentals of electronics, communications and computer sciences, 01 Apr. 2005

  
• An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability

  HAMAMOTO Koichi; FUKETA Hiroshi; HASHIMOTO Masanori; MITSUYAMA Yukio; ONOYE Takao

  IEICE technical report, 26 Jun. 2008

  
• On Evaluation Methods of nMOS Level Shifter Circuits

  OTSU Makoto; TAKAHASHI Shingo; TSUKIYAMA Shuji; HASHIMOTO Masanori; SHIRAKAWA Isao

  IEICE technical report, 20 Mar. 2008

  
• Timing Verification Considering Manufacturing and Environmental Variability

  HASHIMOTO Masanori

  IEICE technical report, 24 Oct. 2007

  
• Self-heating in short intra-block wires

  新開 健一; 橋本 昌宜; 尾上 孝雄

  回路とシステム軽井沢ワークショップ論文集, 23 Apr. 2007

  
• Statistical timing analysis considering spatially correlated dynamic power supply noise

  榎並 孝司; 二宮 進有; 橋本 昌宜

  回路とシステム軽井沢ワークショップ論文集, 23 Apr. 2007

  
• Measurement of Delay Variation Due to Inductive Coupling Noise in 90nm Global Interconnects

  OGASAHARA Yasuhiro; HASHIMOTO Masanori; ONOYE Takao

  電子情報通信学会技術研究報告. CPM, 電子部品・材料, 11 Jan. 2007

  
• Effectiveness of Ground Plane and Shield Wires for Reduction of Coupling Capacitance and Simplification of Capacitance Estimation in System on Panel Circuits

  UCHIDA YOSHIHIRO; TANI SADAHIRO; HASHIMOTO MASANORI; TSUKIYAMA SHUJI; SHIRAKAWA ISAO

  IPSJ journal, 15 Jun. 2006

  
• A-3-4 On a Design Method of Sampling Circuits for Liquid Crystal Displays

  高橋真吾; 築山 修治; 橋本 昌宜; 白川 功

  Proceedings of the Society Conference of IEICE, 2005

  
• Evaluation of processor architecture for energy efficient subthreshold operation

  KURODA DAN; FUKETA HIROSHI; HASHIMOTO MASANORI; ONOYE TAKAO

  IEICE technical report, 08 Oct. 2009

  
• Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing

  原田 諒; 密山 幸男; 橋本 昌宜; 尾上 孝雄

  研究報告システムLSI設計技術（SLDM）, 19 Nov. 2012

  
• A design procedure for oscillator-based physical random number generator with stochastic behavior modeling

  天木 健彦; 橋本 昌宜; 密山 幸男

  IEICE technical report, 29 Nov. 2010

  
• A design procedure for oscillator-based physical random number generator with stochastic behavior modeling

  天木 健彦; 橋本 昌宜; 密山 幸男

  IEICE technical report, 29 Nov. 2010

  
• Evaluation of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures

  KONOURA Hiroaki; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 05 May 2011

  
• Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation

  TAKAI Yasumichi; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 09 Dec. 2010

  
• Measurement Circuits for Acquiring SET Pulse Width Distribution with Fine Time Resolution

  HARADA Ryo; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 20 Sep. 2010

  
• Measurement and Evaluation of Delay Variation Due to Inductive and Capacitive Coupling Noise

  OGASAHARA Yasuhiro; HASHIMOTO Masanori; ONOYE Takao

  Technical report of IEICE. SDM, 11 Aug. 2005

  
• Representative Frequency for Interconnect R(f)L(f)C Extraction

  TSUCHIYA Akira; HASHIMOTO Masanori; ONODERA Hidetoshi

  IEICE Trans. Fundamentals, A, 01 Dec. 2003

  
• Crosstalk Noise Estimation for Generic RC Trees

  HASHIMOTO Masanori; TAKAHASHI Masao; ONODERA Hidetoshi

  IEICE Trans. Fundamentals, A, 01 Dec. 2003

  
• Paper Writing Guide for International Conferences : Implications in VLSI design methodology field

  HASHIMOTO Masanori

  Technical report of IEICE. VLD, 22 Nov. 2010

  
• A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits

  HASHIMOTO Masanori; ONODERA Hidetoshi; TAMARU Keikichi

  IEICE Trans. Fund., A, 25 Jan. 1999

  
• Application Design of Multi-Standard Decoder on Media-Centric Reconfigurable Architecture

  MITSUYAMA Yukio; TAKAHASHI Kazuma; IMAI Rintaro; HASHIMOTO Masanori; ONOYE Takao; SHIRAKAWA Isao

  The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A, 01 Jun. 2010

  
• A Design Procedure for Oscillator-Based Physical Random Number Generator with Stochastic Behavior Modeling

  天木 健彦; 橋本 昌宜; 密山 幸男; 尾上 孝雄

  研究報告システムLSI設計技術（SLDM）, 22 Nov. 2010

  
• AS-1-4 Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability

  Hashimoto Masanori; Fuketa Hiroshi; Onoye Takao

  Proceedings of the IEICE General Conference, 02 Mar. 2010

  
• Evaluation of processor architecture for energy efficient subthreshold operation

  KURODA DAN; FUKETA HIROSHI; HASHIMOTO MASANORI; ONOYE TAKAO

  研究報告システムLSI設計技術（SLDM）, 09 Oct. 2009

  
• Layout Aware Cell Clustering for Body Biasing

  HAMAMOTO Koichi; HASHIMOTO Masanori; MITSUYAMA Yukio; ONOYE Takao

  IEICE technical report, 04 Mar. 2009

  
• Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits

  FUKETA Hiroshi; HASHIMOTO Masanori; MITSUYAMA Yukio; ONOYE Takao

  IEICE technical report, 04 Mar. 2009

  
• Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation

  KANAMOTO Toshiki; AKUTSU Shigekiyo; NAKABAYASHI Tamiyo; ICHINOMIYA Takahiro; HACHIYA Koutaro; KUROKAWA Atsushi; ISHIKAWA Hiroshi; MUROMOTO Sakae; KOBAYASHI Hiroyuki; HASHIMOTO Masanori

  IEICE transactions on fundamentals of electronics, communications and computer sciences, 01 Dec. 2006

  
• An analytic evaluation on soft error immunity enhancement due to temporal triplication

  土井 龍太郎; 橋本 昌宜; 尾上 孝雄

  研究報告システムとLSIの設計技術（SLDM）, 19 Nov. 2014

  
• Placement and routing for enhancing fault avoidance by dynamically partial reconfiguration

  郡浦 宏明; 密山 幸男; 橋本 昌宜; 尾上 孝雄

  研究報告システムLSI設計技術（SLDM）, 08 Mar. 2014

  
• Toward VLSI Reliability Enhancement by Reconfigurable Architecture

  尾上 孝雄; 橋本 昌宜; 密山 幸男; Dawood Alnajjar; 郡浦 宏明

  研究報告システムLSI設計技術（SLDM）, 20 Nov. 2013

  
• Coarse-Grained Reconfigurable Architecture with Flexible Reliability

  KO Younghun; ALNAJJAR Dawood; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  情報処理学会研究報告システムLSI設計技術（SLDM）, 10 Nov. 2008

  
• An Optimal Design Method of Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays

  TAKAHASHI Shingo; TSUKIYAMA Shuji; HASHIMOTO Masanori; SHIRAKAWA Isao

  The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A, 01 Mar. 2008

  
• Coarse-Grained Reconfigurable Architecture with Flexible Reliability

  KO Younghun; ALNAJJAR Dawood; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 10 Nov. 2008

  
• 性能ばらつきを克服する適応的電圧制御の設計と製造後テスト手法

  増田豊; 橋本昌宜

  電子情報通信学 会LSI とシステムのワークショップ, May 2018

  
• Design and test of adaptively voltage scaled circuits

  Y. Masuda; M. Hashimoto

  SIGDA Student Research Forum at 23rd Asia and South Pacic Design Automation Conference, Jan. 2018, Peer-reviewed

  
• マージンの最小化に向けた適応的速度制御の設計と性能評価

  増田豊; 橋本昌宜; 尾上孝雄

  STARC フォーラム2015, Nov. 2015

  
• A-3-5 On Stochastic modeling of NBTI induced threshold voltage variation

  Sato Masahiro; Izuka Syoichi; Awano Hiromitsu; Hashimoto Masanori; Onoye Takao

  Proceedings of the IEICE General Conference, 24 Feb. 2015

  
• B-18-48 Performance evaluation of human detection with thermopile infrared sensor

  Masuda Ryohei; Hashimoto Masanori; Onoye Takao

  Proceedings of the IEICE General Conference, 24 Feb. 2015

  
• クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定

  鵜川 翔平; 信田 龍哉; 橋本 昌宜; 伊藤 雄一; 尾上 孝雄

  研究報告ヒューマンコンピュータインタラクション（HCI）, 07 Jan. 2015

  
• An analytic evaluation on soft error immunity enhancement due to temporal triplication

  DOI Ryutaro; HASHIMOTO Masanori; ONOYE Takao

  Technical report of IEICE. VLD, 26 Nov. 2014

  
• リアルタイム3次元モデリングシステムiClayの実現に向けた1mm3級センサノードの要素技術開発

  KONO Jin; UKAWA Shohei; SHINADA Tatsuya; TSUKAMOTO Mizuho; TANAKA Yuki; NAKAJIMA Kosuke; ITOH Yuichi; HIROSE Tetsuya; HASHIMOTO Masanori

  電子情報通信学会 集積回路研究専門委員会 LSIとシステムのワークショップ2014, May 2014

  
• Placement and routing for enhancing fault avoidance by dynamically partial reconfiguration

  KONOURA HIROAKI; MITSUYAMA YUKIO; HASHIMOTO MASANORI; ONOYE TAKAO

  IEICE technical report. Dependable computing, 15 Mar. 2014

  
• Evaluating a sequential 3D node localization method based on node-to-node distance information

  UKAWA Shohei; SHINADA Tatsuya; ITOH Yuichi; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report. Circuits and systems, 06 Mar. 2014

  
• Adaptive Performance Compensation with On-Chip Variation Monitoring

  HASHIMOTO Masanori

  Technical report of IEICE. ICD, 28 Jan. 2014

  
• 5.1 Time Dependent Degradation(5. Time-Dependent Degradation in Device Characteristics,Dependable VLSI System)

  SATO Takashi; HASHIMOTO Masanori

  The journal of Reliability Engineering Association of Japan, 01 Dec. 2013

  
• Time Dependent Degradation (Invited)

  T. Sato; M. Hashimoto

  The Journal of Reliability Engineering Association of Japan, Dec. 2013, Peer-reviewed, Invited

  
• Toward VLSI Reliability Enhancement by Reconfigurable Architecture

  ONOYE Takao; HASHIMOTO Masanori; MITSUYAMA Yukio; ALNAJJAR Dawood; KONOURA Hiroaki

  IEICE technical report. Dependable computing, 20 Nov. 2013

  
• A Study on Electrode Configuration for Distance Estimation based on Capacitive Coupling between Sensor Nodes

  SHINADA Tatsuya; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report. Communication systems, 14 Mar. 2013

  
• Self-Compensation of Manufacturing Variability using On-Chip Sensors

  HIGUCHI Yuma; HASHIMOTO Masanori; ONOYE Takao

  Technical report of IEICE. VLD, 04 Mar. 2013

  
• A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling

  AMAKI Takehiko; HASHIMOTO Masanori; MITSUYAMA Yukio; ONOYE Takao

  Technical report of IEICE. VLD, 04 Mar. 2013

  
• An observational study on fault-avoidance methods using dynamic partial reconfiguration

  KONOURA Hiroaki; IMAGAWA Takashi; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report, 20 Nov. 2012

  
• neutron Induced Single Event Multiple Transients With Voltage Scaling and body Biasing

  HARADA Ryo; MITSUYAMA Yukio; HASHIMOTO Masanori; ONOYE Takao

  IEICE technical report. Dependable computing, 19 Nov. 2012

  
• A-3-6 An On-chip Real-time Supply Voltage Sensor for Debugging Electrical Timing Failures

  Ueno Miho; Hashimoto Masanori; Onoye Takao

  Proceedings of the Society Conference of IEICE, 28 Aug. 2012

  
• 微細CMOSタイミング設計の新しいコーナー削減手法

  小谷 憲; 増田 弘生; 成木 保文; 奥村 隆昌; 城間 誠; 金本 俊幾; 古川 且洋; 山中 俊輝; 小笠原 泰弘; 佐藤 高史; 橋本 昌宜; 黒川 敦; 田中 正和

  DA シンポジウム, Aug. 2012

  
• 微細プロセス(22nm世代)における配線コーナー削減手法の検討

  城間 誠; 山中 俊輝; 小笠原 泰弘; 金本 俊幾; 成木 保文; 奥村 隆昌; 増田 弘生; 古川 且洋; 佐藤 高史; 橋本 昌宜; 黒川 敦; 田中 正和

  DA シンポジウム, Aug. 2012

  
• A-1-20 Improvement of Efficiency by Reduction in Reverse Current of Differential-Drive CMOS Rectifier

  Tsukamoto M.; Hirose T.; Osaki Y.; Kuroki N.; Numa M.; Hashimoto M.

  Proceedings of the IEICE General Conference, 06 Mar. 2012

  
• Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling

  HOMJAKOVS Igors; HASHIMOTO Masanori; HIROSE Tetsuya; ONOYE Takao

  Technical report of IEICE. ICD, 15 Dec. 2011

  
• An Oscillator-Based True Random Number Generator with Jitter Amplifier

  AMAKI Takehiko; HASHIMOTO Masanori; ONOYE Takao

  Technical report of IEICE. ICD, 15 Dec. 2011

  
• Ultra Low Voltage Subthreshold Circuit Design

  HASHIMOTO Masanori

  IEICE technical report. Dependable computing, 28 Nov. 2011

  
• CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析

  佐方 剛; 成木 保文; 奥村 隆昌; 金本 俊幾; 増田 弘生; 佐藤 高史; 橋本 昌宜; 古川 且洋; 田中 正和; 山中俊輝

  DA シンポジウム, Aug. 2011

  
• RTNを考慮した回路特性ばらつき解析方法の検討

  増田 弘生; 佐方 剛; 佐藤 高史; 橋本 昌宜; 古川 且洋; 田中 正和; 山中 俊輝; 金本俊幾

  DA シンポジウム, Aug. 2009

  
• 電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法

  榎並 孝司; 橋本 昌宜; 佐藤 高史

  信学技報 VLSI設計技術研究会, Mar. 2009

  
• Decoupling Capacitance Allocation for Timing With Statistical Noise Model and Timing Analysis

  T. Enami; M. Hashimoto; T. Sato

  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2008, Peer-reviewed

  
• チップ内システマティックばらつきと回路スキュー特性相関

  増田 弘生; 大川 眞一; 黄田 剛; 奥村 隆昌; 黒川 敦; 増田 弘生; 金本 俊幾; 佐藤 高史; 橋本 昌宜; 高藤 浩資; 中島 英斉; 小野 信任

  第21回 回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

  
• 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案

  奥村 隆昌; 黒川 敦; 増田 弘生; 金本 俊幾; 佐藤 高史; 橋本 昌宜; 高藤 浩資; 中島 英斉; 小野 信任

  第21回 回路とシステム軽井沢ワークショップ, Apr. 2008, Peer-reviewed

  
• Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for in-Site Soc Power Integrity Verification

  Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, 2008

  
• Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification

  Yasuhiro Ogasahara; Masanori Hashimoto; Takao Onoye

  2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008

  
• Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement

  Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato; Takao Onoye

  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Oct. 2007

  
• 45-65nm ノードにおける遅延ばらつき特性の環境温度依存性

  中林 太美世; 黒川 敦; 佐藤 高史; 橋本 昌宜; 増田 弘生

  第20回 回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

  
• 統計的 STA でのスルー依存性を考慮した遅延ばらつき計算手法の提案

  高藤 浩資; 小林 宏行; 小野 信任; 増田 弘生; 中島 英斉; 奥村 隆昌; 橋本 昌宜; 佐藤 高史

  第20回 回路とシステム軽井沢ワークショップ, Apr. 2007, Peer-reviewed

  
• 電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現

  小笠原 泰弘; 榎並 孝司; 橋本 昌宜; 佐藤 高史; 尾上 孝雄

  信学技報, Jan. 2007

  
• Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement

  IEEE Trans. on Circuits and Systems—II: Express Briefs, 2007

  
• Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated With Full-chip Simulation

  Y. Ogasahara; T. Enami; M. Hashimoto; T. Sato; T. Onoye

  IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006, Peer-reviewed

  
• 統計的 STA の精度検証手法

  小林 宏行; 小野 信任; 佐藤 高史; 岩井 二郎; 橋本 昌宜

  DA シンポジウム, Jul. 2006

  
• Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction

  International Workshop on Compact Modeling, 2006

  
• A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations

  ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2006

  
• 電源ノイズ解析のための回路動作部表現法の評価

  2006年電子情報通信学会総合大会講演論文集, 2006

  
• Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction

  International Workshop on Compact Modeling, 2006

  
• A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process Variations

  ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2006

  
• 画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術

  電子情報通信学会 VLSI設計技術研究会, 2006

  
• ロードマップに準拠したSPICEトランジスタモデルの構築

  2006年電子情報通信学会総合大会講演論文集, 2006

  
• 統計的STAの有効性の検証手法

  第19回 回路とシステム(軽井沢)ワークショップ, 2006

  
• 電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル

  第19回 回路とシステム(軽井沢)ワークショップ, 2006

  
• LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測

  第19回 回路とシステム(軽井沢)ワークショップ, 2006

  
• Estimation for Equivalent Parallel Resistance of LC Oscillators Including Resitance Components of MOSFETs

  S. Uemura; M. Hashimoto; H. Onodera

  IEICE Society Conference, 21 Sep. 2005

  
• オンチップ伝送線路の基板損失に対する下層配線の影響

  土谷亮; 橋本昌宜; 小野寺秀俊

  2005年電子情報通信学会総合大会, 24 Mar. 2005

  
• Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion

  T. Sato; M. Hashimoto; H. Onodera

  ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

  
• On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design

  T. Sato; J. Ichimiya; N. Ono; K. Hachiya; M. Hashimoto

  ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

  
• Timing Analysis Considering Temporal Supply Voltage Fluctuation

  M. Hashimoto; J. Yamaguchi; T. Sato; H. Onodera

  ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2005, Peer-reviewed

  
• Measurement and analysis of delay variation due to inductive coupling

  Proc. IEEE Custom Integrated Circuits Conference, 2005

  
• CMLを用いたオンチップ長距離高速信号伝送技術の開発

  第9回システムLSIワークショップ, 2005

  
• An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads

  T. Sato; M. Hashimoto; H. Onodera

  The 12th workshop on synthesis and system integration of mixed information technologies (SASIMI), Oct. 2004, Peer-reviewed

  
• 微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--

  橋本昌宜; 小野寺秀俊

  2004年電子情報通信学会ソサイエティ大会講演論文集, 23 Sep. 2004

  
• Equivalent Waveform Propagation for Static Timing Analysis

  IEEE Trans. on CAD, 2004

  Access this misc :

  
• Design and Optimization of CMOS Current Mode Logic Dividers

  Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004

  
• Performance Limitation of On-chip Global Interconnects for High-speed Signaling

  Proc. IEEE Custom Integrated Circuits Conference, 2004

  
• Equivalent, waveform propagation for static timing analysis

  Hashimoto M; Yamada Y; Onodera H

  IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004

  Access this misc :

  
• Performance limitation of on-chip global interconnects for high-speed signaling

  A Tsuchiya; Y Gotoh; M Hashimoto; H Onodera

  PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004

  
• オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---

  2004

  
• Equivalent Waveform Propagation for Static Timing Analysis

  IEEE Trans. on CAD, 2004

  Access this misc :

  
• 配線RL抽出におけるリターンパス選択手法

  2004

  
• 遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価

  2004

  
• フロアプランにおけるオンチップ熱ばらつきの解析と対策

  2004

  
• オンチップインダクタンスを考慮したLSI電源配線網解析

  2004

  
• Design and optimization of CMOS current mode logic dividers

  A Shinmyo; M Hashimoto; H Onodera

  PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004

  
• Performance Limitation of On-chip Global Interconnects for High-speed Signaling

  Proc. IEEE Custom Integrated Circuits Conference, 2004

  
• A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits

  Masanori HASHIMOTO; Hidetoshi ONODERA

  2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, 01 Oct. 2000

  

Books and Other Publications

• Book chapter, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design, VLSI Design and Test for Systems Dependability

  T. Sato; M. Hashimoto; S. Tanakamaru; K. Takeuchi; Y. Sato; S. Kajihara; M. Yoshimoto; J. Jung; Y. Kimi; H. Kawaguchi; H. Shimada; J. Yao, Joint work

  Springer, Aug. 2018, Not refereed

  Find Kyoto University's collection of books :

  
• Book chapter, Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space, VLSI Design and Test for Systems Dependability

  H. Hihara; A. Iwasaki; M. Hashimoto; H. Ochi; Y. Mitsuyama; H. Onodera; H. Kanbara; K. Wakabayashi; T. Sugibayashi; T. Takenaka; H. Hada; M. Tada, Joint work

  Springer, Aug. 2018, Not refereed

  Find Kyoto University's collection of books :

  
• Book chapter, Radiation-Induced Soft Errors, VLSI Design and Test for Systems Dependability

  E. Ibe; S. Yoshimoto; M. Yoshimoto; H. Kawaguchi; K. Kobayashi; J. Furuta; Y. Mitsuyama; M; Hashimoto,T. Onoye; H. Kanbara; H. Ochi; K. Wakabayashi; H. Onodera; M. Sugihara, Joint work

  Springer, Aug. 2018, Not refereed

  Find Kyoto University's collection of books :

  

Industrial Property Rights

• 特開7284465, 特願PCT/JP2019/032455, 信号線の接続方法、プログラム、及び、半導体集積回路

  橋本昌宜; 土井龍太郎; 劉 載勲

  

Works

• ネット家電の実用化・普及のためのホームゲートウェイ集積化技術開発

  From 2004

  

Media Coverage

• 一般的な中性子源で、半導体ソフトエラー率を評価

  EE Times Japan, Jun. 2023, Internet

  
• 正/負ミュオンや中性子などのソフトエラーの違いをソシオネクストなどが確認

  正/負ミュオンや中性子などのソフトエラーの違いをソシオネクストなどが確認, Jul. 2021, Internet

  
• EE Times Japan

  EE Times Japan, Jul. 2021, Internet

  
• ＦＰＧＡにブレークスルーか チップ面積が１／１０未満 に

  日経エレクトロニクス, Apr. 2020, Paper

  
• A flexible brain for AI

  AlphaGalileo, Mar. 2020, Internet

  
• A flexible brain for AI

  EurekAlert!, Mar. 2020, Internet

  
• ビアスイッチでプログラムするFPGA チップを開発

  EE Times Japan, Feb. 2020, Internet

  
• FPGA にブレークスルーか、ビア・スイッチで論理回路面 積を1/10 未満に

  日経クロステック, Feb. 2020, Internet

  
• 阪大、FPGA の実装密度を12 倍向上させる「ビアスイッチ」を開発

  PC Watch, Feb. 2020, Internet

  
• チップのプログラム量12 倍に

  日経産業新聞, Feb. 2020, Paper

  
• 阪大、次世代のFPGA チップにトランジスタを用いず12 倍の高密度化実装に成功

  日経新聞, Feb. 2020, Internet

  
• 12 倍の実装密度書き換え可能集積回路

  日刊工業新聞, Feb. 2020, Paper

  
• 宇宙線ミュオンで電子機器に悪影響

  科学技術新聞, Jun. 2018, Paper

  
• 宇宙線「ミュオン」の影響確認

  日刊工業新聞, Jun. 2018, Paper

  
• 九大と阪大など、「宇宙線ミュオン」が電子機器の誤 作動を引き起こすことを解明

  日本経済新聞, May 2018, Internet

  
• 損傷してもエラー修正

  日刊工業新聞, Aug. 2011, Paper

  

External funds: Kakenhi

• Muon-induced soft error evaluation platform: future prediction based on measurement and simulation

  Grant-in-Aid for Scientific Research (S)

  Broad Section J

  Kyoto University

  橋本 昌宜

  From 26 Jun. 2019, To 31 Mar. 2024, Granted

  ソフトエラー;ミューオン;集積システム;VLSI;信頼性

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-19H05664/
• Development of Deep Neural Network Accelerator Utilizing Approximate Computing

  Grant-in-Aid for Scientific Research (B)

  Basic Section 60040:Computer system-related

  Tokyo Institute of Technology

  JAEHOON YU

  From 01 Apr. 2019, To 31 Mar. 2022, Project Closed

  深層ニューラルネットワーク;近似コンピューティング;深層学習;推論アクセラレータ;アクセラレータ;NPU;ニューラルネットワーク;ハードウェアアクセラレータ;近似計算;電力効率;Deep Neural Network;蒸留;訓練データ削減

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-19H04079/
• Development of technical platform for estimation of muon-induced soft error rates in semiconductor devices

  Grant-in-Aid for Scientific Research (B)

  Kyushu University

  Yukinobu Watanabe

  From 01 Apr. 2016, To 31 Mar. 2019, Project Closed

  ミューオン;半導体デバイス;照射試験;シングルイベントアップセット;宇宙線ミューオン計測;粒子輸送シミュレーション;PHITS;加速試験;輸送シミュレーション

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-16H03906/
• Development of mm-cubic wirelessly-powerd sensor node and its application to tangible user interface

  Grant-in-Aid for Scientific Research (A)

  Osaka University

  Masanori Hashimoto

  From 01 Apr. 2015, To 31 Mar. 2018, Project Closed

  センサノード;実世界ユーザインタフェース;無線給電;実世界ユーザーインタフェース

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15H01679/
• iClay: A 3D real-time modeling system with tiny sensor nodes

  Grant-in-Aid for Scientific Research (A)

  Osaka University

  Masanori HASHIMOTO

  From 01 Apr. 2011, To 31 Mar. 2014, Project Closed

  3次元モデリング;センサネットワーク;リアルタイムモデリング;極小センサノード

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23240015/
• Development of a sensor-node processor with four order of magnitude variable power dissipation

  Grant-in-Aid for Young Scientists (A)

  Osaka University

  Masanori HASHIMOTO

  From 01 Apr. 2007, To 31 Mar. 2010, Project Closed

  ハードウェア設計;センサネットワーク;サブスレッショルド回路;超低消費電力;製造ばらつき;性能補償;基板バイアス;動的タイミング変動;プロセッサ;レイアウト方式

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-19680002/
• Reconfigurable architecture with flexible dependability

  Grant-in-Aid for Scientific Research (B)

  Osaka University

  Takao ONOYE

  From 01 Apr. 2007, To 31 Mar. 2009, Project Closed

  計算機アーキテクチャ;ディペンダビリティ;再構成可能アーキテクチャ;再構成可能集積回路;ソフトエラー;製造ばらつき;冗長化;暗号化;自己診断;動作隠蔽;ディベンダビリティ

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-19300011/
• 超微細LSIにおける遅延変動要因を考慮した静的遅延解析手法の開発

  Grant-in-Aid for Young Scientists (B)

  Kyoto University

  橋本 昌宜

  From 01 Apr. 2002, To 31 Mar. 2004, Project Closed

  遅延解析;電源線ノイズ;配線特性;RLC抽出;ゲート遅延モデル;等価入力波形;波形伝播;静的遅延解析;遅延不確かさ;遅延変動;製造ばらつき;クロストークノイズ;インダクタンス;抵抗性容量遮蔽効果;LSI配線

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-14750261/
• Research of a High-speed Signal Transmission Scheme for Integrated Circuits

  Grant-in-Aid for Scientific Research (B)

  KYOTO UNIVERSITY

  Hidetoshi ONODERA

  From 01 Apr. 2002, To 31 Mar. 2005, Project Closed

  高速信号伝送;LSI;SerDes;配線特性;高速信号伝達;オンチップ伝送線路;PLL;LC型PLL;リング型PLL;性能予測;RLC抽出;LSI配線;伝送線路;配線構造;ドライバ駆動力;スパイラルインダクタ;応答局面法, Signal Transmission;LSI;SerDes

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-14350186/
• 動き補償を利用した動画像の実時間背景・対象物分離アルゴリズムとハードウエアの開発

  Grant-in-Aid for Scientific Research on Priority Areas

  Science and Engineering

  Kyoto University

  小野寺 秀俊

  From 01 Apr. 2001, To 31 Mar. 2003, Project Closed

  動き補償;ジャイロセンサ;動きベクトル;動画像

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13023206/
• Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

  Grant-in-Aid for Scientific Research (B)

  KYOTO UNIVERSITY

  Hidetoshi ONODERA

  From 01 Apr. 1999, To 31 Mar. 2002, Project Closed

  製造ばらつき;統計解析;統計的遅延解析;チップ内ばらつき;チップ間ばらつき;VLSI;階層設計;アナログ回路;統計的解析;ばらつき;集積回路;歩留り最大化;ロバスト設計;設計容易化技術;統計モデリング;モンテカルロ解析, Manufacturing Variability;Statistical Analysis;Statistical Timing Analysis;Intra-Chip Variability;Inter-Chip Variability;VLSI;Hierarchical Design;Analog Circuit

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11555095/
• Development of foundational technology for reliability assessment of next-generation integrated systems to overcome cosmic ray-induced malfunctions

  Grant-in-Aid for Scientific Research (S)

  Broad Section J

  Kyoto University

  橋本 昌宜

  From 01 Apr. 2024, To 31 Mar. 2029, Granted

  ソフトエラー;宇宙線;超伝導回路;集積回路;信頼性

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-24H00073/

External funds: others

• 計算機システム関連分野に関する学術研究動向 (2022年度分)

  Japan Society for the Promotion of Science (JSPS), 学術研究動向等に関する調査研究

  From 01 Apr. 2022, To 31 Mar. 2023

  代表者
• 「計算機システム関連分野に関する学術研究動向」 (2021年度分)

  Japan Society for the Promotion of Science (JSPS), 学術動向研究等調査研究

  From 01 Apr. 2021, To 31 Mar. 2022

  代表者
• 耐量子計算機性秘匿計算に基づくセキュア情報処理基盤

  CREST

  From 01 Oct. 2019, To 31 Mar. 2025

  本間尚文
• 光ニューラルネットワークの時空間ダイナミクスに基づく計算基盤技術

  CREST

  From 01 Apr. 2019, To 31 Mar. 2024

  鈴木秀幸
• 安全・安心・スマートな長寿社会実現のための高度な量子アプリケーション技術の創出

  OPERA

  From 01 Oct. 2017, To 31 Mar. 2022

  中野貴志

Education

Teaching subject(s)

• From 01 Apr. 2024, To 31 Mar. 2025

  Logic Circuits

  6012, Spring, Faculty of Engineering, 2
• From 01 Apr. 2024, To 31 Mar. 2025

  Integraged Circuits Engineering

  6113, Spring, Faculty of Engineering, 2
• From 01 Apr. 2024, To 31 Mar. 2025

  Digital Circuits

  6060, Spring, Faculty of Engineering, 2
• From 01 Apr. 2024, To 31 Mar. 2025

  Integrated Circuits Engineering, Adv.

  3631, Spring, Graduate School of Informatics, 2
• From 01 Apr. 2023, To 31 Mar. 2024

  Integraged Circuits Engineering

  6113, Spring, Faculty of Engineering, 2
• From 01 Apr. 2023, To 31 Mar. 2024

  Digital Circuits

  6060, Spring, Faculty of Engineering, 2
• From 01 Apr. 2023, To 31 Mar. 2024

  Logic Circuits

  6012, Spring, Faculty of Engineering, 2
• From 01 Apr. 2023, To 31 Mar. 2024

  Integrated Circuits Engineering, Adv.

  3631, Spring, Graduate School of Informatics, 2
• From 01 Apr. 2022, To 31 Mar. 2023

  Integrated Circuits Engineering, Adv.

  3631, Spring, Graduate School of Informatics, 2
• From 01 Apr. 2022, To 31 Mar. 2023

  Introduction to Electronics

  5300, Spring, Faculty of Engineering, 2
• From 01 Apr. 2022, To 31 Mar. 2023

  Integraged Circuits Engineering

  6113, Spring, Faculty of Engineering, 2
• From 01 Apr. 2022, To 31 Mar. 2023

  Digital Circuits

  6060, Spring, Faculty of Engineering, 2
• From 01 Apr. 2022, To 31 Mar. 2023

  Logic Circuits

  6012, Spring, Faculty of Engineering, 2
• From Apr. 2021, To Mar. 2022

  Introduction to Electronics

  Spring, 工学部
• From Apr. 2021, To Mar. 2022

  Digital Circuits

  Spring, 工学部
• From Apr. 2021, To Mar. 2022

  Logic Circuits

  Spring, 工学部
• From Apr. 2021, To Mar. 2022

  Integraged Circuits Engineering

  Spring, 工学部
• From Apr. 2021, To Mar. 2022

  Integrated Circuits Engineering, Adv.

  Spring, 情報学研究科

Participation in PhD Defense

• Leakage-Current-Aware Layout Design of DNTT-Based OTFTs and Its Applications to Digital Circuits

  OSHIMA KUNIHIRO, Graduate School of Informatics, Sub-chief Examiner

  25 Mar. 2024
• Studies on Synthesis Methods for Efficient Optical Logic Circuits

  MATSUO RYOSUKE, Graduate School of Informatics, Sub-chief Examiner

  23 Mar. 2023
• Robust Design of Low-voltage OTFT Circuits for Flexible Electronic Systems

  QIN ZHAOXING, Graduate School of Informatics, Sub-chief Examiner

  23 Mar. 2023
• 電力変換回路におけるパワーモジュールの熱設計に向けた特性測定とモデリング

  NAKAMURA YOHEI, Graduate School of Informatics, Sub-chief Examiner

  23 Mar. 2023
• Design and Verification of Single-Flux-Quantum Digital Circuits Using Clocked and Clockless Gates

  KAWAGUCHI TAKAHIRO, Graduate School of Informatics, Sub-chief Examiner

  23 Jan. 2023

Participation in PhD Defenses (other than KU)

• Study on CMOS LSI Systems for Solar-Cell-Powered Continuous Glucose Monitoring Contact Lenses

  CHEN Guowei, Nagoya University, Japan, Sub-chief Examiner

  01 Jan. 2023

Administration

Faculty management (title, position)

• From 01 Apr. 2023, To 31 Mar. 2025

  工学部教育制度委員会　委員
• From 01 Apr. 2023, To 31 Mar. 2025

  企画委員会委員
• From 01 Apr. 2021, To 31 Mar. 2023

  教務委員会委員