Basic Information

Faculty

• 工学部

Professional Memberships

• INFORMATION PROCESSING SOCIETY OF JAPAN
• IEEE Computer Society

Academic Degree

• (Keio University)
• (Keio University)

Academic Resume (Graduate Schools)

• 慶應義塾大学, 大学院理工学研究科前期博士課程開放環境科学専攻, 修了
• 慶應義塾大学, 大学院理工学研究科後期博士課程開放環境科学専攻, 修了

Academic Resume (Undergraduate School/Majors)

• 慶應義塾大学, 理工学部情報工学科, 卒業

High School

• High School

  慶應義塾志木高等学校

Research History

• From Dec. 2021, To Present

  Kyoto University, Graduate School of Informatics, 助教
• From Apr. 2019, To Nov. 2021

  Hiroshima University, 情報科学部, 特任助教

Profile

• Profile

  2014年 慶應義塾大学 理工学部 情報工学科 卒業。2019年 同大学 大学院 理工学研究科 博士課程修了（研究活動において理工学研究科の範となる業績をあげた学生を顕彰する「藤原賞」受賞）。博士（工学）。同年より広島大学 情報科学部 特任助教。2021年より、京都大学 大学院情報学研究科 助教（工学部 情報学科 兼担）。現在に至る。

  
  

  2016〜2019年 国立情報学研究所 特別共同利用研究員。2017年6月〜9月 英国Imperial College London 研究滞在。2020年 広島大学AI・データイノベーション教育研究センター 社会人リカレント教育オンライン講座 講師。2019年より、電子情報通信学会 コンピュータ・システム研究会（CPSY）専門委員。2019〜2021年 International Symposium on Computing and Networking (CANDAR) Local Arrangement Chair。2023年 International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) Publication Chair。情報処理学会、IEEE Computer Society各会員。2016年度 情報処理学会 山下記念研究賞、IEEE Computer Society Young Author Award 2018 等受賞。

  
  

  現在まで並列計算機の相互結合網、並列計算、再構成可能コンピューティング等の研究に従事。最近はアニーリング計算（QUBO）を含む分野融合型AIコンピューティング基盤、光の極限性能を活かすコンピューティング等の研究に着手。

Language of Instruction

• Japanese
• English

ID,URL

• J-Global ID

  201901008569079027

Website(s) (URL(s))

• http://lab3.kuis.kyoto-u.ac.jp/~yasudo/

researchmap URL

• https://researchmap.jp/yasudo

Research

Research Interests

• QUBO
• アニーリング
• GPU
• 並列計算
• 相互結合網
• FPGA
• 計算機アーキテクチャ

Research Areas

• Informatics, High-performance computing
• Informatics, Information theory
• Informatics, Computer systems

Papers

• Power Optimized Design Framework for FPGA Clusters

  Kensuke Iizuka; Kohei Ito; Ryota Yasudo; Hideharu Amano

  IPSJ Transactions on System and LSI Design Methodology, Jun. 2024, Peer-reviewed

  
• Solving the QAP by Two-Stage Graph Pointer Networks and Reinforcement Learning

  Satoko Iida; Ryota Yasudo

  arXiv, Mar. 2024, Corresponding author

  
• A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks

  Ryota Miyagi; Ryota Yasudo; Kentaro Sano; Hideki Takase

  ACM Transactions on Reconfigurable Technology and Systems, 2024, Peer-reviewed

  
• Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints

  Masashi Oda; Kai Keida; Ryota Yasudo

  International Symposium on Computing and Networking, Nov. 2023, Peer-reviewed, Last author, Corresponding author

  
• Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing

  Ryota Yasudo

  2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), Mar. 2023, Peer-reviewed, Lead author, Corresponding author

  Access this paper :

  
• Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension

  Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura

  International Solid-State Circuits Conference (ISSCC), Feb. 2023, Peer-reviewed

  
• Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning

  Ryota Miyagi; Ryota Yasudo; Kentaro Sano; Hideki Takase

  International Conference on Field Programmable Technology (FPT), Dec. 2022, Peer-reviewed

  
• Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches

  Kohei Ito; Ryota Yasudo; Hideharu Amano

  International Conference on Field Programmable Logic and Applications (FPL), Aug. 2022, Peer-reviewed, Corresponding author

  
• GPU-accelerated Scalable Solver with Bit Permutated Cyclic-Min Algorithm for Quadratic Unconstrained Binary Optimization

  Ryota Yasudo; Koji Nakano; Yasuaki Ito; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano

  Journal of Parallel and Distributed Computing, 2022, Peer-reviewed, Lead author

  
• Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs

  Ryota Yasudo; Koji Nakano; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Shiro Ozaki; Takashi Yazane; Kenichiro Hamano

  International Workshop on Advances in Parallel and Distributed Computational Models (APDCM), May 2022, Peer-reviewed, Lead author

  
• Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer

  Tomohiro Imanaga; Koji Nakano; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Shiro Ozaki; Takashi Yazane; Kenichiro Hamano

  International Symposium on Computing and Networking, Nov. 2021, Peer-reviewed

  
• Simple Iterative Iterative Search for the Maximum Independent Set Problem Optimized for the GPUs

  Tomohiro Imanaga; Koji Nakano; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano

  Concurrency and Computation: Practice and Experience, 2021, Peer-reviewed

  
• High-throughput FPGA Implementation for Quadratic Unconstrained Binary Optimization

  Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano

  Concurrency and Computation: Practice and Experience, 2021, Peer-reviewed

  
• Analytical Performance Estimation for Large-scale Reconfigurable Dataflow Platforms

  Ryota Yasudo; Jose Gabriel de Figueiredo Coutinho; Ana Lucia Varbanescu; Wayne Luk; Hideharu Amano; Tobias Becker; Ce Guo

  ACM Transactions on Reconfigurable Technology and Systems, 2021, Peer-reviewed, Lead author

  
• Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA

  Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano

  International Symposium on Computing and Networking, Nov. 2020, Peer-reviewed

  
• Efficient GPU Implementation for Solving the Maximum Independent Set Problem

  Tomohiro Imanaga; Koji Nakano; Masaki Tao; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano

  International Symposium on Computing and Networking, Nov. 2020, Peer-reviewed

  
• Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs

  Ryota Yasudo; Koji Nakano; Yasuaki Ito; Masaru Tatekawa; Ryota Katsuki; Takashi Yazane; Yoko Inaba

  Proc. of the International Conference on Parallel Processing, Aug. 2020, Peer-reviewed, Lead author

  
• A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation

  Masaki Tao; Koji Nakano; Yasuaki Ito; Ryota Yasudo; Masaru Tatekawa; Ryota Katsuki; Takashi Yazane; Yoko Inaba

  22nd International Workshop on Advances in Parallel and Distributed Computational Models, May 2020, Peer-reviewed

  
• Body Bias Optimization for Real-Time Systems

  Carlos C. Cortes Torres; Ryota Yasudo; Hideharu Amano

  J. Low Power Electron. Appl., Feb. 2020, Peer-reviewed

  
• Designing Low-Diameter Interconnection Networks with Multi-ported Host-Switch Graphs

  Ryota Yasudo; Koji Nakano; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano

  Concurrency and Computation: Practice and Experience, 2020, Peer-reviewed, Lead author

  
• Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks

  Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano

  IEICE Transactions on Information and Systems, 2020, Peer-reviewed

  
• Dual-Plane Isomorphic Hypercube Network

  Takeo Hosomi; Ryota Yasudo; Michihiro Koibuchi; Shinji Shimojo

  International Conference on High Performance Computing in Asia Pacific Region, Jan. 2020, Peer-reviewed

  
• Folded Bloom Filter for High Bandwidth Memory, with GPU implementations

  Masatoshi Hayashikawa; Koji Nakano; Yasuaki Ito; Ryota Yasudo

  International Symposium on Computing and Networking, Nov. 2019, Peer-reviewed

  
• The Degree/Diameter Problem for Host-Switch Graphs

  Ryota Yasudo; Koji Nakano

  International Workshop on Parallel and Distributed Algorithms and Applications, in conjunction with CANDAR 2019, Nov. 2019, Peer-reviewed, Lead author

  
• Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA

  Takuma Wada; Naoki Matsumura; Ryota Yasudo; Koji Nakano; Yasuaki Ito

  Concurrency and Computation: Practice and Experience, Aug. 2019, Peer-reviewed

  
• Designing High-Performance Interconnection Networks with Host-Switch Graphs

  Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano

  IEEE Trans. Parallel Distrib. Syst., Feb. 2019, Peer-reviewed, Lead author

  
• A Generalized Theory based on the Turn Model for Deadlock-Free Irregular Networks

  Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano

  IEICE Transactions on Information and Systems, 2019, Peer-reviewed

  
• Theoretical Design Methodology for Practical Interconnection Networks

  Ryota Yasudo

  Keio University, Jan. 2019, Peer-reviewed

  
• Performance Estimation for Exascale Reconfigurable Dataflow Platforms

  Ryota Yasudo; Jose Gabriel Figueiredo Continho; Ana Lucia Varbanescu; Wayne Luk; Hideharu Amano; Tobias Becker

  International Conference on Field-Programmable Technology, Dec. 2018, Peer-reviewed, Lead author

  
• k-Optimized Path Routing for High-Throughput Data Center Networks.

  Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano

  Sixth International Symposium on Computing and Networking, CANDAR 2018, Nov. 2018, Peer-reviewed

  
• HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

  Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano

  Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS, 29 May 2018, Peer-reviewed

  
• Performance Prediction for Large-Scale Heterogeneous Platforms.

  Ryota Yasudo; Ana Lucia Varbanescu; José Gabriel; F. Coutinho; Wayne Luk; Hideharu Amano

  26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Apr. 2018, Peer-reviewed, Lead author

  
• 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

  Hiroshi Nakahara; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi

  Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017, 27 Nov. 2017, Peer-reviewed

  
• XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs

  H. Nakahara; Ng Anh Vu Doan; R. Yasudo; H. Amano

  2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, 19 Oct. 2017, Peer-reviewed

  
• Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

  Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano

  Proceedings of the International Conference on Parallel Processing, 01 Sep. 2017, Peer-reviewed, Lead author

  
• Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

  Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura

  IEEE TRANSACTIONS ON COMPUTERS, Apr. 2017, Peer-reviewed, Lead author

  
• On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

  Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura

  Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, 28 Sep. 2015, Peer-reviewed, Lead author

  
• Design of a Low Power NoC Router using Marching Memory Through type

  Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura

  2014 EIGHTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2014, Peer-reviewed, Lead author

  
• A low power NoC router using the marching memory through type

  Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanebe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura

  2014 IEEE COOL CHIPS XVII, 2014, Peer-reviewed, Lead author

  

Misc.

• 東工大とJST、複数の計算原理を使い分けるアニーリングプロセッサを開発

  波留久泉

  マイナビニュース, Feb. 2023

  
• An Efficient NoC with Decentralized Routers

  安戸 僚汰; 松谷 宏紀; 鯉渕 道紘

  電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 19 Jan. 2016

  
• より具体的な条件設定のホスト-スイッチグラフ部門を新設！ 未来スパコンのネットワーク構成を発見するコンペ 「グラフ ゴルフ」を復活して開催

  国立情報学研究所 ニュースリリース, Apr. 2021

  
• 組合せ最適化問題の新解法「アダプティブ・バルク・サーチ」

  矢実 貴志

  DATA INSIGHT, Sep. 2020

  
• NTTデータと広島大、組み合わせ問題で新計算方式

  矢口竜太郎

  日本経済新聞 電子版, Aug. 2020

  
• NTTデータと広島大学、組み合わせ最適化問題をGPUで高速に解く新手法を開発

  中田 敦

  日経クロステック, Aug. 2020

  
• NTTデータと広島大、組合せ最適化問題をGPUで高速解決する技術

  宇都宮 充

  PC Watch, Aug. 2020

  
• GPUの計算性能を最大限活用する組合せ最適化問題の新解法を公開

  株式会社NTTデータ ニュースリリース, Aug. 2020

  
• 【研究成果】GPUの計算能力を最大限活用する組合せ最適化問題の新解法〜1兆探索/秒を超えるアダプティブ・バルク・サーチ〜

  広島大学ニュースリリース, Aug. 2020

  
• 研究会推薦博士論文速報 Theoretical Design Methodology for Practical Interconnection Networks

  安戸僚汰

  情報処理学会 研究会推薦博士論文速報, Jul. 2019

  

Presentations

• 離散最適化と機械学習の融合領域における研究紹介

  安戸僚汰

  【第7回】富士通次世代コンピューティングセミナー, 25 Jun. 2024, Invited

  
• 並列アニーリング計算の原理と応用：FPGA，ASIC，GPUの事例

  安戸僚汰

  第63回組込みシステム研究発表会, 14 Jul. 2023, Invited

  
• 大規模な再構成可能データフロー計算基盤の数理的性能推定

  安戸僚汰

  第21回情報科学技術フォーラム（FIT2022）, イベント企画「トップカンファレンスセッション6-1 ソフトウェア理解とコンピュータアーキテクチャ」, 15 Sep. 2022, Invited

  
• 複数GPUによる組合せ最適化問題QUBOの新解法アダプティブ・バルク・サーチ

  安戸僚汰

  第20回情報科学技術フォーラム（FIT），イベント企画「トップコンファレンスセッション4-1 コンピュータシステム」, 26 Aug. 2021, Invited

  
• GPUを駆使した二次無制約二値最適化問題の高速解法

  安戸僚汰

  日本オペレーションズ・リサーチ学会 4部会・グループ合同研究会, 17 Oct. 2020, Invited

  
• Degree/Diameter Problem for Host-Switch Graphs

  Ryota Yasudo

  第15回 情報科学ワークショップ（WTCS2019）, 18 Sep. 2019

  
• ホストスイッチグラフによる高性能相互結合網の設計

  安戸 僚汰

  第18回情報科学技術フォーラム（FIT）トップコンファレンスセッション7 コンピュータシステム, 05 Sep. 2019, Invited

  
• Graph-theoretic Perspective on Network Topology for Supercomputers

  Ryota Yasudo

  First mini Symposium on Computing and Networking, 04 Jun. 2019, Invited

  
• 高スループットな相互結合網のためのスケーラブルな複数経路選択手法

  河野隆太; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴

  電子情報通信学会技術研究報告, Dec. 2018

  
• Interconnection Networks with the Optimal Number of Switches and the Optimal Host Distribution

  Ryota Yasudo

  CANDAR Extreme Infrastructure Workshop, Nov. 2018, Invited

  
• Graph-Theoretic Approach for Designing Low-Latency Interconnection Networks

  Ryota Yasudo

  第14回 情報科学ワークショップ（WTCS2018）, Sep. 2018

  
• ルーティングアルゴリズムによる通信帯域の測定と理解

  河野隆太; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴

  電子情報通信学会技術研究報告, Jul. 2018

  
• ターンモデルベースの不規則網向けルーティング

  河野隆太; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴

  電子情報通信学会技術研究報告, Nov. 2017

  
• ホストとスイッチから成る相互結合網の理論モデル

  安戸僚汰; 鯉渕道紘; 天野英晴; 中野浩嗣

  電子情報通信学会技術研究報告, Dec. 2016

  
• 可変次数列を持つ相互結合網の構成法

  安戸 僚汰

  第15回 情報科学技術フォーラム（FIT2016）, Sep. 2016

  
• 高次数規則トポロジの3D-NoCへのレイアウト

  中原浩; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴

  第15回 情報科学技術フォーラム（FIT2016）, Sep. 2016

  
• 非正則グラフによる低遅延相互結合網の検討

  安戸僚汰; 藤原一毅; 鯉渕道紘; 松谷宏紀; 天野英晴; 中村維男

  電子情報通信学会技術研究報告, Aug. 2016

  
• 3D-NoCトポロジにおける消費エネルギー・平均最短距離最適化

  中原浩; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 中野浩嗣; 天野英晴

  情報処理学会 第78回全国大会, Mar. 2016

  
• 分散ルータによる高性能NoC

  安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴; 中村維男

  情報処理学会研究報告, Jan. 2016

  
• 三次元積層チップにおける最大配線長制限下トポロジ最適化

  中原浩; 藤木大地; 蓼誠一; 安戸僚汰; 河野隆太; 松谷宏紀; 鯉渕道紘; 中野浩嗣; 天野英晴

  電子情報通信学会技術研究報告, Dec. 2015

  
• 三次元積層チップへの高性能既存トポロジレイアウト法

  中原浩; 安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴

  電子情報通信学会技術研究報告, Aug. 2015

  
• トランスペアレントラッチを用いたNoC向け分散ルータアーキテクチャ

  安戸僚汰; 松谷宏紀; 鯉渕道紘; 天野英晴; 中村維男

  電子情報通信学会技術研究報告, Nov. 2014

  
• マーチングメモリスルータイプを用いたNoCルータ

  安戸僚汰; 加賀美崇紘; 天野英晴; 中瀬泰伸; 渡邊政志; 大石 司; 清水 徹; 中村維男

  電子情報通信学会技術研究報告, Nov. 2013

  

External funds: Kakenhi

• 超並列システム向け可逆データ圧縮法の提案と実用化

  Grant-in-Aid for Scientific Research (B)

  Basic Section 60050:Software-related

  Hiroshima University

  中野 浩嗣

  From 01 Apr. 2021, To 31 Mar. 2025, Granted

  データ圧縮;ビッグデータ処理;並列処理;機械学習

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-21H03417/
• データ駆動型社会に向けた大容量高速メモリキューブ・ネットワークの研究

  Grant-in-Aid for Early-Career Scientists

  Basic Section 60040:Computer system-related

  Kyoto University;Hiroshima University

  安戸 僚汰

  From 01 Apr. 2020, To 31 Mar. 2024, Granted

  メモリネットワーク;メモリキューブ;相互結合網;計算機システム

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-20K19770/
• 極限光技術を生かすフォトニック近似コンピューティング

  Grant-in-Aid for Transformative Research Areas (A)

  Transformative Research Areas, Section (IV)

  National Institute of Informatics

  鯉渕 道紘

  From 16 Jun. 2022, To 31 Mar. 2027, Granted

  相互結合網;フォトニックコンピューティング;近似コンピューティング

  https://kaken.nii.ac.jp/grant/KAKENHI-PLANNED-22H05193/
• Multi-Disciplinary AI Computing Platform Based on Hyper-dimensional Vector Representation

  Grant-in-Aid for Scientific Research (S)

  Broad Section J

  Tokyo Institute of Technology

  本村 真人

  From 12 Apr. 2023, To 31 Mar. 2028, Granted

  深層ニューラルネット;アニーリング計算;ハイパーディメンジョナルコンピューティング;機械学習;離散最適化

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23H05489/
• アニーリングマシンを基礎とした近似的意思決定システムの研究

  Grant-in-Aid for Early-Career Scientists

  Basic Section 60040:Computer system-related

  Kyoto University

  安戸 僚汰

  From 01 Apr. 2024, To 31 Mar. 2027, Granted

  アニーリングマシン;意思決定;最適化;強化学習

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-24K20754/
• 超並列システム向け可逆データ圧縮法の提案と実用化

  Grant-in-Aid for Scientific Research (B)

  Basic Section 60050:Software-related

  Hiroshima University

  中野 浩嗣

  From 01 Apr. 2021, To 31 Mar. 2025, Granted

  データ圧縮;並列処理;ビッグデータ処理;機械学習

  https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-23K21655/

Education

Teaching subject(s)

• From 01 Apr. 2024, To 31 Mar. 2025

  Computer Science Laboratory and Exercise 2

  9022, Fall, Faculty of Engineering, 2
• From 01 Apr. 2024, To 31 Mar. 2025

  Parallel Computer Architecture

  3657, Spring, Graduate School of Informatics, 2
• From 01 Apr. 2024, To 31 Mar. 2025

  Computer Science Laboratory and Exercise 3

  9084, Spring, Faculty of Engineering, 4
• From 01 Apr. 2023, To 31 Mar. 2024

  Computer Science Laboratory and Exercise 2

  9022, Fall, Faculty of Engineering, 2
• From 01 Apr. 2023, To 31 Mar. 2024

  Computer Science Laboratory and Exercise 3

  9084, Spring, Faculty of Engineering, 4
• From 01 Apr. 2022, To 31 Mar. 2023

  Computer Science Laboratory and Exercise 3

  9084, Spring, Faculty of Engineering, 4
• From 01 Apr. 2022, To 31 Mar. 2023

  Computer Science Laboratory and Exercise 2

  9022, Fall, Faculty of Engineering, 2

Academic, Social Contribution

Committee Memberships

• From 2023, To Present

  International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Publication Chair
• From 2022, To Present

  International Workshop on Parallel and Distributed Algorithms and Applications in conjunction with International Symposium on Computing and Networking, Program Committee
• From 2022, To Present

  International Symposium on Computing and Networking, Program Committee
• From 2022, To Present

  The cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG), Program Committee
• From 2021, To Present

  International Workshop on Advances in Parallel and Distributed Computational Models (APDCM) in conjunction with IEEE International Parallel and Distributed Processing Symposium (IPDPS), Program Committee
• From 2020, To Present

  International Workshop on Computer Systems and Architectures in conjunction with International Symposium on Computing and Networking (CANDAR), Program Committee
• From Jun. 2019, To Present

  専門委員, 電子情報通信学会コンピュータシステム研究会
• From 2019, To 2021

  International Symposium on Computing and Networking, Local Arrangement Chair
• From 2019

  International Workshop on Sustainable Computing Systems in conjunction with International Symposium on Computing and Networking (CANDAR), Program Committee

Social Contribution

• 社会人リカレント教育オンライン講座 Pythonで始めるプログラミング・データ分析

  Lecturer

  広島大学 AI・データイノベーション教育研究センター, From Nov. 2020, To Dec. 2020